Semiconductor device

Abstract

Disclosed is a semiconductor device comprising a substrate including first and second active patterns, first and second channel patterns on the first and second active patterns and each including first and second semiconductor patterns, first source/drain patterns connected to the first channel pattern, second source/drain patterns connected to the second channel pattern, a first inner gate electrode between neighboring first semiconductor patterns, a second inner gate electrode between neighboring second semiconductor patterns, a first inner gate spacer between the first inner gate electrode and the first source/drain pattern, and a second inner gate spacer between the second inner gate electrode and the second source/drain pattern. The first inner gate spacer has a first thickness. The second inner gate spacer has a second thickness. The first thickness is greater than the second thickness.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate that includes a first active pattern and a second active pattern;   a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first and second channel patterns including a first semiconductor pattern and a second semiconductor pattern that are vertically spaced apart from each other;   a plurality of first source/drain patterns connected to the first channel pattern and spaced apart from each other in a first direction;   a plurality of second source/drain patterns connected to the second channel pattern and spaced apart from each other in the first direction;   a first inner gate electrode between neighboring ones of the first semiconductor patterns;   a second inner gate electrode between neighboring ones of the second semiconductor patterns;   a first inner gate spacer between the first inner gate electrode and a first source/drain pattern of the plurality of first source/drain patterns; and   a second inner gate spacer between the second inner gate electrode and a second source/drain pattern of the plurality of second source/drain patterns,   wherein the first inner gate spacer has a first thickness in the first direction,   wherein the second inner gate spacer has a second thickness in the first direction, and   wherein the first thickness is greater than the second thickness.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein the first thickness ranges from about 2.5 nm to about 3 nm, and   wherein the second thickness ranges from about 1.5 nm to about 2 nm.   
     
     
         3 . The semiconductor device of  claim 1 ,
 wherein the first source/drain patterns include silicon (Si), and   wherein the second source/drain patterns include silicon-germanium (SiGe).   
     
     
         4 . The semiconductor device of  claim 1 , further comprising a high-k dielectric layer between the first inner gate electrode and the first inner gate spacer and between the second inner gate electrode and the second inner gate spacer. 
     
     
         5 . The semiconductor device of  claim 1 ,
 wherein the first source/drain patterns are spaced apart at a first length from each other in the first direction,   wherein the second source/drain patterns are spaced apart at a second length from each other in the first direction, and   wherein the first length is greater than the second length.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the first inner gate spacer includes:
 a first dielectric pattern that surrounds the first inner gate electrode; and   a second dielectric pattern on the first dielectric pattern,   wherein the second dielectric pattern is in contact with the first source/drain pattern, and   wherein the first dielectric pattern and the second dielectric pattern include the same or different dielectric materials.   
     
     
         7 . The semiconductor device of  claim 6 , further comprising:
 a high-k dielectric layer between the first inner gate electrode and the first inner gate spacer and between the second inner gate electrode and the second inner gate spacer,   wherein the first dielectric pattern is in contact with the high-k dielectric layer between the first inner gate electrode and the first inner gate spacer, and   wherein the second dielectric pattern is spaced apart from the first inner gate electrode.   
     
     
         8 . The semiconductor device of  claim 6 , wherein the first dielectric pattern and the second dielectric pattern include silicon oxide. 
     
     
         9 . The semiconductor device of  claim 6 ,
 wherein the first dielectric pattern includes silicon nitride, and   wherein the second dielectric pattern includes silicon oxide.   
     
     
         10 . The semiconductor device of  claim 6 ,
 wherein a thickness in the first direction of the first dielectric pattern is about 50% to about 60% of the first thickness, and   wherein a thickness in the first direction of the second dielectric pattern is about 40% to about 50% of the first thickness.   
     
     
         11 . The semiconductor device of  claim 6 , wherein a sum of thicknesses in the first direction of the first dielectric pattern and the second dielectric pattern is substantially the same as the first thickness. 
     
     
         12 . The semiconductor device of  claim 6 , wherein the first dielectric pattern includes:
 a first protective pattern on the first inner gate electrode; and   a second protective pattern on the first protective pattern,   wherein the second protective pattern is between the first protective pattern and the second dielectric pattern, and   wherein the second protective pattern includes a material different from a material of the second dielectric pattern.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the second protective pattern is in contact with the second dielectric pattern. 
     
     
         14 . The semiconductor device of  claim 1 ,
 wherein the second source/drain patterns include silicon-germanium (SiGe),   wherein the second inner gate spacer includes:
 a first protective pattern that surrounds the second inner gate electrode; and 
 a first dielectric pattern on the first protective pattern, 
   wherein the first dielectric pattern is in contact with the first source/drain pattern,   wherein the first protective pattern includes silicon nitride, and   wherein the first dielectric pattern includes silicon oxide.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the first protective pattern is between the first dielectric pattern and the second inner gate electrode. 
     
     
         16 . A semiconductor device, comprising:
 a substrate that includes a first active pattern and a second active pattern;   a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first and second channel patterns including a plurality of semiconductor patterns that are vertically spaced apart from each other;   a plurality of first source/drain patterns connected to the first channel pattern;   a plurality of second source/drain patterns connected to the second channel pattern;   a first inner gate electrode between neighboring ones of the plurality of semiconductor patterns of the first channel pattern;   a second inner gate electrode between neighboring ones of the plurality of semiconductor patterns of the second channel pattern;   a first inner gate spacer between the first inner gate electrode and the first source/drain pattern; and   a second inner gate spacer between the second inner gate electrode and the second source/drain pattern,   wherein, at the same level, a spacing distance between the first inner gate electrode and a neighboring one of the plurality of first source/drains pattern is greater than a spacing distance between the second inner gate electrode and a neighboring one of the plurality of second source/drain patterns.   
     
     
         17 . The semiconductor device of  claim 16 ,
 wherein each of the first source/drain patterns includes silicon (Si),   wherein each of the second source/drain patterns includes silicon-germanium (SiGe), and   wherein the first inner gate spacer and the second inner gate spacer include at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.   
     
     
         18 . A semiconductor device, comprising:
 a substrate that includes a first active pattern and a second active pattern;   a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first and second channel patterns including a plurality of semiconductor patterns that are vertically spaced apart from each other;   a plurality of first source/drain patterns connected to the first channel pattern;   a plurality of second source/drain patterns connected to the second channel pattern;   a first gate electrode on the plurality of semiconductor patterns of the first channel pattern, the first gate electrode including a first inner gate electrode between neighboring ones of the plurality of semiconductor patterns of the first channel pattern and a first outer gate electrode on an uppermost one of the plurality of semiconductor patterns of the first channel pattern;   a second gate electrode on the plurality of semiconductor patterns of the second channel pattern, the second gate electrode including a second inner gate electrode between neighboring ones of the plurality of semiconductor patterns of the second channel pattern and a second outer gate electrode on an uppermost one of the plurality of semiconductor patterns of the second channel pattern;   a first inner gate spacer between one first source/drain pattern of the plurality of first source/drain patterns and a lateral surface of the first inner gate electrode; and   a second inner gate spacer between one second source/drain pattern of the plurality of second source/drain patterns and a lateral surface of the second inner gate electrode,   wherein a thickness of the first inner gate spacer is in a range of about 2.5 nm to about 3 nm, and   wherein a thickness of the second inner gate spacer is in a range of about 1.5 nm to about 2 nm.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the first inner gate spacer includes:
 a first dielectric pattern that surrounds the first inner gate electrode; and   a second dielectric pattern on the first dielectric pattern,   wherein the second dielectric pattern is in contact with the one first source/drain pattern.   
     
     
         20 . The semiconductor device of  claim 19 ,
 wherein the first dielectric pattern is spaced apart from the one first source/drain pattern, and   wherein the first dielectric pattern and the second dielectric pattern include silicon oxide.