Contact structure, semiconductor device with the same, and method for fabricating the same

Abstract

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a bottom contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; a liner layer positioned between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of partition layers; and a top contact layer positioned on the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

What is claimed is: 
     
         1 . A cell contact structure, comprising:
 a bottom contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers;   a liner layer positioned between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of partition layers; and   a top contact layer positioned on the bottom contact layer and the liner layer;   wherein a top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar;   wherein the liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium;   wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride.   
     
     
         2 . The cell contact structure of  claim 1 , wherein the top contact layer comprises tungsten, titanium, or titanium nitride. 
     
     
         3 . The cell contact structure of  claim 1 , wherein the top contact layer comprises the same material as the bottom contact layer. 
     
     
         4 . The cell contact structure of  claim 1 , wherein the liner layer comprises n-type dopants or p-type dopants. 
     
     
         5 . The cell contact structure of  claim 1 , wherein a top surface of the top contact layer is lower than top surfaces of the plurality of bit line structures. 
     
     
         6 . A semiconductor device, comprising:
 a substrate;   two bit line structures may be formed on the substrate, extending along a first direction, and separated from each other;   two partition layers positioned on the substrate, extending along a second direction perpendicular to the first direction, separated from each other along the first direction, and simultaneously contacting the two bit line structures; and   a cell contact structure comprising:
 a bottom contact layer positioned on the substrate and enclosed by the two bit line structures and the two partition layers; 
 a liner layer positioned between the substrate and the bottom contact layer, between the two bit line structures and the bottom contact layer, and between the two partition layer and the bottom contact layer; and 
 a top contact layer positioned on the liner layer and the bottom contact layer; 
   wherein a top surface of the liner layer and a top surface of the bottom contact layer are substantially coplanar;   wherein the liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium;   wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the top contact layer comprises tungsten, titanium, or titanium nitride. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the top contact layer comprises the same material as the bottom contact layer. 
     
     
         9 . The semiconductor device of  claim 6 , wherein a top surface of the top contact layer is lower than top surfaces of the plurality of bit line structures. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the liner layer comprises n-type dopants or p-type dopants. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the bottom contact layer comprises a rectangular or square-shaped cross-sectional profile in a top-view perspective. 
     
     
         12 . The semiconductor device of  claim 9 , further comprising a plurality of spacer structures positioned between the cell contact structure and the two bit line structures. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the plurality of spacer structures respectively comprises a bit line inner spacer positioned between one of the two bit line structures and the cell contact structure, a bit line middle spacer positioned between the bit line inner spacer and the cell contact structure, and a bit line outer  20  spacer positioned between the bit line middle spacer and the cell contact structure. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the bit line inner spacer comprises silicon nitride. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the bit line middle spacer comprises silicon oxide. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the bit line outer spacer comprises silicon nitride. 
     
     
         17 . The semiconductor device of  claim 12 , wherein the plurality of spacer structures respectively comprises a bit line inner spacer positioned between one of the two bit line structures and the cell contact structure, a bit line outer spacer positioned between the bit line inner spacer and the cell contact structure, and an air gap positioned between the bit line inner spacer and the bit line outer spacer. 
     
     
         18 . The semiconductor device of  claim 12 , further comprising a bottom dielectric layer positioned between the two bit line structures and the substrate, between the plurality of spacer structures and the substrate, and between the two partition layers and the substrate. 
     
     
         19 . The semiconductor device of  claim 18 , wherein the two bit line structures respectively comprises:
 a bottom conductive layer positioned on the bottom dielectric layer;   a bit line middle conductive layer positioned on the bottom conductive layer;   a bit line top conductive layer positioned on the bit line middle conductive layer; and   a bit line capping layer positioned on the bit line top conductive layer.   
     
     
         20 . The semiconductor device of  claim 19 , wherein top surfaces of the plurality of spacer structures and top surfaces of the two bit line structures are substantially coplanar.