Reservation Station Design Method FOR Vector Execution Units

Abstract

A reservation station design method for vector execution units includes: S1, receiving an instruction by a reservation station, decoding the number of ticks for executing the instruction, and extracting an address of each source operand; S2, determining whether each source operand is ready; selecting a specific instruction slot to store the instruction, monitoring a bypass path, and pulling up a status bit of each not-ready source operand; S3, sorting non-transmitted instructions, determining a specific instruction according to a sorting result, and transmitting the specific instruction to a vector execution unit, and sending out a prewrite-back signal; and S4, setting hold signals, and blocking an instruction to be blocked; and when the address of each source operand corresponding to any one non-transmitted instruction is identical with an address in the prewrite-back signal, counting ticks, and in the last tick, transmitting a corresponding non-transmitted instruction to the vector execution unit for execution.

What is claimed is: 
     
         1 . A reservation station design method for vector execution units, wherein a dpu module, a reservation station, a register file and a vector execution unit are connected in sequence, a bypass path is connected to the reservation station, the reservation station comprises a plurality of instruction slots, and the register file comprises a plurality of registers;
 the reservation station design method comprises the following steps:   S1, in any one tick of the reservation station, receiving, by the reservation station, an instruction dispatched from the dpu module and getting ready configuration parameters, decoding a number of ticks for executing the instruction, and extracting an address of each source operand of the instruction;   S2, determining each source operand according to the address of each source operand extracted in S1, determining whether each source operand is ready, and pulling up a status bit of each ready source operand;   selecting a specific instruction slot from the plurality of instruction slots to store the instruction, monitoring the bypass path, and when it is detected that an address of each not-ready source operand is hit by an address in written-back data, pulling up a status bit of each not-ready source operand;   S3, sorting all non-transmitted instructions in the plurality of instruction slots in S2 according to a sequence in which the instructions enter the reservation station, and determining whether there is an instruction that is not blocked in the non-transmitted instructions; when there is no instruction that is not blocked in the non-transmitted instructions, not transmitting any instruction; when there is an instruction that is not blocked in the non-transmitted instructions, determining a specific instruction that enters the reservation station at the earliest and is not blocked according to a sorting result, transmitting the specific instruction to the vector execution unit for execution, and sending out a prewrite-back signal; and   S4, setting a group of hold signals, detecting each non-transmitted instruction in the plurality of instruction slots in S3 by the group of hold signals, determining each instruction to be blocked and each instruction not to be blocked, and blocking each instruction to be blocked;   getting ready configuration parameters corresponding to each non-transmitted instruction, and pulling up a status bit of each source operand corresponding to each non-transmitted instruction; and when the address of each source operand corresponding to any one non-transmitted instruction is identical with an address in the prewrite-back signal in S3, counting ticks, and in a last tick, transmitting a corresponding non-transmitted instruction to the vector execution unit for execution.   
     
     
         2 . The reservation station design method according to  claim 1 , wherein in S1, the instruction dispatched from the dpu module has a serial number of a branch prediction block, and whether pipeline flushing is needed for the instruction is determined according to the serial number of the branch prediction block. 
     
     
         3 . The reservation station design method according to  claim 1 , wherein in S1, one or at least two reservation stations are configured, and a number of the one or at least two reservation stations is same as a number of vector execution units. 
     
     
         4 . The reservation station design method according to  claim 1 , wherein in S2, a method for determining whether each source operand is ready comprises: detecting whether each source operand has been written back into the register file, determining each source operand that has been written back into the register file as ready, and determining each source operand that has not been written back into the register file as not-ready. 
     
     
         5 . The reservation station design method according to  claim 1 , wherein in S2, a method for selecting the specific instruction slot from the plurality of instruction slots to store the instruction comprises:
 determining whether an instruction slot, where an instruction in a previous tick is stored, has a vacant position; when the instruction slot, where the instruction in the previous tick is stored, has the vacant position, storing the instruction in S2 in the vacant position of the instruction slot where the instruction in the previous tick is stored; when the instruction slot, where the instruction in the previous tick is stored, does not have the vacant position, determining whether other instruction slots other than the instruction slot, where the instruction in the previous tick is stored, has the vacant position;   when other instruction slots have the vacant position, selecting one instruction slot with the vacant position to store the instruction in S2; when other instruction slots do not have the vacant position, storing the instruction in S2 in an instruction slot that transmits an instruction in the previous tick.   
     
     
         6 . The reservation station design method according to  claim 1  wherein in S2, the status bit is pulled up by a positive logic, “1” indicates a high position, and “0” indicates a low position. 
     
     
         7 . The reservation station design method according to  claim 1 , wherein in S4, the group of hold signals comprises a write conflict block signal, a division block signal and a write-back bubble block signal, and the division block signal is written back by the write-back bubble block signal; and in a case where a division block or a write conflict block is detected when the plurality of instruction slots are detected by the group of hold signals, transmission of an instruction corresponding to the division block or the write conflict block is stopped.