Gate-all-around transistor having multiple gate lengths

Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped active region over a substrate and comprising a number of channel layers interleaved by a number of sacrificial layers, removing a source/drain region of the fin-shaped active region to form a source/drain opening, forming a source/drain feature in the source/drain opening, selectively removing the number of sacrificial layers to form a number of gate openings, and forming a gate structure in the number of gate openings, where the gate structure includes a first portion formed in a first gate opening of the number of gate openings and a second portion formed in a second gate opening of the number of gate openings, a gate length of the first portion is different from a gate length of the second portion.

What is claimed is: 
     
         1 . A method, comprising:
 receiving a structure comprising:
 a fin-shaped active region over a substrate and comprising a plurality of channel layers interleaved by a plurality of sacrificial layers, and 
 a dummy gate stack over a channel region of the fin-shaped active region, 
   removing a source/drain region of the fin-shaped active region to form a source/drain opening;   performing an etching process to selectively recess the plurality of sacrificial layers to form inner spacer recesses;   forming inner spacer features in the inner spacer recesses;   forming a source/drain feature in the source/drain opening;   selectively removing the dummy gate stack to form a gate trench;   selectively removing the plurality of sacrificial layers to form a plurality of gate openings; and   forming a gate structure in the gate trench and the plurality of gate openings, wherein the gate structure comprises a first portion formed in a first gate opening of the plurality of gate openings and a second portion formed in a second gate opening of the plurality of gate openings, a gate length of the first portion is different from a gate length of the second portion.   
     
     
         2 . The method of  claim 1 , wherein a gate length of a portion of the gate structure formed in the gate trench is less than the gate length of the first portion. 
     
     
         3 . The method of  claim 1 , wherein the first gate opening is disposed under the second gate opening, and the gate length of the first portion is greater than the gate length of the second portion. 
     
     
         4 . The method of  claim 1 , wherein the plurality of sacrificial layers comprise a bottommost sacrificial layer and a topmost sacrificial layer over the bottommost sacrificial layer, and a germanium concentration of the topmost sacrificial layer is different than a germanium concentration of the bottommost sacrificial layer. 
     
     
         5 . The method of  claim 4 , wherein etchant of the etching process etches the topmost sacrificial layer at a rate higher than it etches the bottommost sacrificial layer. 
     
     
         6 . The method of  claim 4 , wherein the selectively removing of the bottommost sacrificial layer and the topmost sacrificial layer of the plurality of sacrificial layers forms the first gate opening and the second gate opening respectively, and the second gate opening spans a width greater than the first gate opening. 
     
     
         7 . The method of  claim 1 , wherein the structure further comprises a gate spacer extending along a sidewall surface of the dummy gate stack, wherein a width of the gate spacer is greater than a width of a widest inner spacer feature of the inner spacer features. 
     
     
         8 . The method of  claim 1 , further comprising:
 before the forming of the source/drain feature, forming a dielectric layer to fill a bottom portion of the source/drain opening, wherein the source/drain feature is over and in direct contact with the dielectric layer.   
     
     
         9 . The method of  claim 1 , further comprising:
 forming a dielectric layer between and in direct with the substrate and the gate structure.   
     
     
         10 . A method, comprising:
 forming a first sacrificial layer over a substrate;   forming a first channel layer over the first sacrificial layer;   forming a second sacrificial layer over the first channel layer, wherein the first sacrificial layer and the second sacrificial layer comprise different compositions;   forming a second channel layer over the second sacrificial layer;   performing a first etching process to laterally recess the first sacrificial layer and the second sacrificial layer at different etch rates;   after the performing of the first etching process, performing a second etching process to selectively remove the laterally recessed first sacrificial layer and the second sacrificial layer to form a first gate opening and a second gate opening; and   forming a gate structure in the first gate opening and the second gate opening.   
     
     
         11 . The method of  claim 10 , wherein the first sacrificial layer and the second sacrificial layer comprise silicon germanium, and a germanium concentration of the second sacrificial layer is higher than a germanium concentration of the first sacrificial layer. 
     
     
         12 . The method of  claim 11 , wherein a gate length of a portion of the gate structure formed in the first gate opening is greater than a gate length of a portion of the gate structure formed in the second gate opening. 
     
     
         13 . The method of  claim 12 , wherein the gate structure further comprises a top portion formed over the second channel layer, a gate length of the top portion of the gate structure is less than the gate length of the portion of the gate structure formed in the second gate opening. 
     
     
         14 . The method of  claim 10 , further comprising:
 forming a third sacrificial layer over the second channel layer, wherein the first sacrificial layer and the third sacrificial layer comprise a same material but different constituent atomic percentages; and   forming a third channel layer over the third sacrificial layer,   wherein the performing of the first etching process further laterally recesses the third sacrificial layer,   wherein the performing of the second etching process further selectively removes the laterally recessed third sacrificial layer, thereby forming a third gate opening,   wherein the gate structure is further formed in the third gate opening.   
     
     
         15 . The method of  claim 14 , wherein a germanium concentration of the third sacrificial layer is higher than a germanium concentration of the first sacrificial layer. 
     
     
         16 . The method of  claim 14 , wherein a germanium concentration of the third sacrificial layer is higher than a germanium concentration of the second sacrificial layer. 
     
     
         17 . A semiconductor device, comprising:
 a plurality of nanostructures over a substrate;   a source/drain feature coupled to the plurality of nanostructures; and   a gate structure wrapping around and over each of the plurality of nanostructures, wherein the gate structure comprises:
 a first portion disposed under a topmost nanostructure of the plurality of nanostructures and having a first gate length, and 
 a second portion disposed between the substrate and a bottommost nanostructure of the plurality of nanostructures and having a second gate length greater than the first gate length. 
   
     
     
         18 . The semiconductor device of  claim 17 , wherein the gate structure further comprises a top portion over the topmost nanostructure of the plurality of nanostructures and having a gate length less than the first gate length. 
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a gate spacer disposed adjacent to the top portion of the gate structure,   wherein the gate spacer extends over the first portion and second portion of the gate structure.   
     
     
         20 . The semiconductor device of  claim 18 , further comprising:
 a plurality of inner spacer features interleaving the plurality of nanostructures,   wherein a bottommost inner spacer feature of the plurality of inner spacer features has a width less than other inner spacer features of the plurality of inner spacer features.