Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof

Abstract

The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

1 . A semiconductor device, comprising:
 a first epitaxial source/drain feature having a first surface and a second surface, wherein the first epitaxial source/drain feature includes a first type of dopants;   a second epitaxial source/drain feature having a third surface and a fourth surface, wherein the second epitaxial source/drain feature includes a second type of dopants, and the third surface of the second epitaxial source/drain feature faces the first surface of the first epitaxial source/drain feature;   a contact etch stop layer formed along the second surface of the first epitaxial source/drain feature and the fourth surface of the second epitaxial source/drain feature;   an interlayer dielectric (ILD) layer disposed on the contact etch stop layer; and   a mask layer disposed on the first surface of the first epitaxial source/drain feature;   a hybrid fin formed disposed between the first and second epitaxial source/drain features, wherein the hybrid fin is in contact with the contact etch stop layer, the mask layer, and third surface of the second epitaxial source/drain feature.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the mask layer comprises oxides of semiconductor materials. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the mask layer comprises SiGeOx. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a liner disposed between the first source/drain feature and the mask layer.   
     
     
         5 . The semiconductor device of  claim 4 , wherein the liner is a semiconductor layer of a single crystalline material. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the hybrid fin comprises:
 a dielectric liner in contact with the first and second epitaxial source/drain features; and   a dielectric filling material disposed on the dielectric liner.   
     
     
         7 . The semiconductor device of  claim 1 , wherein the first source/drain feature includes n-type dopants. 
     
     
         8 . A method for forming a semiconductor device, comprising:
 forming first and second semiconductor fin structures on a first side of a substrate;   epitaxially growing a first source/drain feature from the first semiconductor fin structure;   forming a mask layer over the first source/drain feature;   epitaxially growing a second source/drain feature from the second semiconductor fin structure while the first source/drain feature is covered by the mask layer, wherein the first and second source/drain features are joined together with a portion of the mask layer disposed in between;   removing an exposed portion of the mask layer;   forming a contact etch stop layer over the first and second source/drain features;   forming an interlayer dielectric layer over the contact etch stop layer;   forming a cut opening between the first and second source/drain features from a second side of the substrate, wherein the contact etch stop layer is exposed at a bottom of the cut opening; and   forming a hybrid fin in the cut opening.   
     
     
         9 . The method of  claim 8 , wherein forming the mask layer on the first source/drain feature comprises:
 forming an epitaxial liner on the first source/drain feature;   forming an epitaxial cap layer on the epitaxial liner;   oxidizing the epitaxial cap layer; and   annealing the oxidized epitaxial cap layer to form the self-aligned mask layer.   
     
     
         10 . The method of  claim 9 , wherein the first epitaxial source/drain feature includes a first type of dopants and the second epitaxial source/drain feature includes a second type of dopants. 
     
     
         11 . The method of  claim 10 , wherein the first epitaxial source/drain feature includes n-type dopants. 
     
     
         12 . The method of  claim 11 , wherein the mask layer comprises oxides of one or more semiconductor elements. 
     
     
         13 . The method of  claim 12 , wherein the epitaxial liner comprises silicon, and epitaxial layer comprises silicon and germanium. 
     
     
         14 . The method of  claim 8 , wherein forming the cut opening comprises:
 removing the first and second semiconductor fin structures to form first and second fin cavities;   forming first and second dielectric fins in the first and second fin cavities; and   forming the cut opening between the first and second dielectric fins.   
     
     
         15 . The method of  claim 14 , further comprising:
 forming sidewall spacers on the first and second dielectric fins prior to forming the cut opening.   
     
     
         16 . The method of  claim 15 , wherein forming the hybrid fin comprises:
 forming a dielectric liner in the cut opening; and   depositing a filling dielectric layer over the dielectric liner.   
     
     
         17 . The method of  claim 8 , further comprising:
 forming a hard mask layer over the second semiconductor fin structure prior to growing the first source/drain feature; and   removing the hard mask layer from the second semiconductor fin structure after forming the mask layer.   
     
     
         18 . A semiconductor device, comprising:
 a first epitaxial source/drain feature having:
 a first side surface; 
 a second side surface opposing the first side surface; and 
 a top surface; 
   a contact etch stop layer disposed on the top surface of the first epitaxial source/drain feature;   a mask layer disposed on the first side surface;   a first hybrid fin facing the mask layer disposed on the first side surface of the first source/drain feature and the contact etch stop layer; and   a second hybrid fin facing the second side surface of the first source/drain feature.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the first hybrid fin contacts the mask layer and the contact etch stop layer and the second hybrid fin contacts the second surface of the first source/drain feature. 
     
     
         20 . The semiconductor device of  claim 18 , wherein the mask layer comprises SiGeOx.