Semiconductor device, and semiconductor package and electronic system including the same

Abstract

A semiconductor device includes a circuit region including a pad region, and a cell region including a memory cell structure on the circuit region. The semiconductor device includes a stacked region where the cell region is stacked on the circuit region and a non-stacked region where the pad region of the circuit region is positioned outside the stacked region. The semiconductor device further includes a plurality of the semiconductor devices stacked atop each other and electrically connected to each other in the pad regions. A bonding layer is between adjacently stacked devices.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a circuit region including a pad region; and   a cell region including a memory cell structure on the circuit region,   wherein the semiconductor device includes a stacked region where the cell region is stacked on the circuit region and a non-stacked region where the pad region of the circuit region is positioned outside the stacked region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein an area of the circuit region is greater than an area of the cell region in a plan view, and
 a thickness of the non-stacked region is less than a thickness of the stacked region.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the pad region includes a through connecting portion including a first portion that passes through at least a partial portion of the circuit region. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the through connecting portion includes
 a bonding structure at a first surface of the circuit region,   the first portion extending from the bonding structure to a second surface of the circuit region opposite to the first surface of the circuit region, and
 a pad at a side of the second surface of the circuit region. 
   
     
     
         5 . The semiconductor device of  claim 1 , wherein the non-stacked region is at a side of one edge of the circuit region in a first direction and extends in a second direction that is transverse to the first direction in a plan view. 
     
     
         6 . The semiconductor device of  claim 5 , wherein a width of the non-stacked region or the pad region in the first direction is less than a width of the stacked region or the cell region in the first direction. 
     
     
         7 . The semiconductor device of  claim 1 , wherein an area of the non-stacked region or an area of the pad region is less than an area of the stacked region or an area of the cell region. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the semiconductor device has a short axis direction and a long axis direction that are transverse to each other in a plan view, and
 the non-stacked region or the pad region is at a side of one edge in the short axis direction and extends in the long axis direction.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the semiconductor device has a short axis direction and a long axis direction that are transverse to each other in a plan view, and
 the non-stacked region or the pad region is at a side of one edge in the long axis direction and extends in the short axis direction.   
     
     
         10 . The semiconductor device of  claim 1 , wherein the semiconductor device has a first direction and a second direction that are transverse to each other in a plan view,
 the non-stacked region includes a first region that is at a side of one edge in the first direction and extends in the second direction, and a second region that is at a side of one edge in the second direction and extends in the first direction, and   the pad region is at a corner portion where the first region and the second region cross each other.   
     
     
         11 . The semiconductor device of  claim 1 , wherein the memory cell structure includes a stacking structure including a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on each other, and a channel structure extending through the stacking structure, and
 where the cell region is bonded to the circuit region.   
     
     
         12 . A semiconductor package, comprising:
 a plurality of semiconductor devices including a first semiconductor device and a second semiconductor device,   wherein the first semiconductor device includes a first stacked region where a first cell region having a first memory cell structure is on a first circuit region and includes a first non-stacked region where a first pad region of the first circuit region is positioned outside the first stacked region,   wherein the second semiconductor device includes a second stacked region where a second cell region having a second memory cell structure is on a second circuit region and includes a second non-stacked region where a second pad region of the second circuit region is positioned outside the second stacked region, and   wherein the first semiconductor device and the second semiconductor device are electrically connected to each other by stacking the second pad region on the first pad region.   
     
     
         13 . The semiconductor package of  claim 12 , wherein a first through connecting portion that passes through at least a partial portion of the first circuit region in the first pad region is electrically connected to a second through connecting portion that passes through at least a partial portion of the second circuit region in the second pad region. 
     
     
         14 . The semiconductor package of  claim 13 , wherein the first or second through connecting portion includes
 a bonding structure at a first surface of the first or second circuit region,   a first portion extending from the bonding structure to a second surface of the first or second circuit region opposite to the first surface of the first or second circuit region, and   a pad at a side of the second surface of the first or second circuit region, and   wherein the bonding structure of the first through connecting portion and the pad of the second through connecting portion are connected to each other through an interconnection member.   
     
     
         15 . The semiconductor package of  claim 12 , wherein an area of the first or second non-stacked region, an area of the first or second pad region, or an area of a connecting region of the first semiconductor device and the second semiconductor device is less than an area of the first or second stacked region, an area of the first or second cell region, or an area of a non-overlapped region of the first semiconductor device and the second semiconductor device. 
     
     
         16 . The semiconductor package of  claim 12 , wherein the first semiconductor device and the second semiconductor device have a symmetrical shape based on the first or second pad region in a plan view. 
     
     
         17 . The semiconductor package of  claim 12 , wherein a distance between the first circuit region and the second circuit region in a thickness direction is less than a thickness of the cell region in the thickness direction. 
     
     
         18 . The semiconductor package of  claim 12 , further comprising:
 a third semiconductor device that includes
 a third stacked region, wherein a third cell region including a third memory cell structure is on a third circuit region, and 
 a third non-stacked region, wherein a third pad region of the third circuit region is positioned outside the third stacked region, 
   wherein the first pad region is at one side of the first semiconductor device in a first direction, the second pad region is at the other side of the second semiconductor device in the first direction, and the third pad region is at the one side of the third semiconductor device in the first direction, and   the first semiconductor device, the second semiconductor device, and the third semiconductor device are electrically connected to each other by sequentially stacking the first pad region, the second pad region, and the third pad region.   
     
     
         19 . The semiconductor package of  claim 12 , further comprising:
 a third semiconductor device that includes
 a third stacked region, wherein a third cell region including a third memory cell structure is on a third circuit region, and 
 a third non-stacked region, wherein a third pad region of the third circuit region is positioned outside the third stacked region; and 
   a fourth semiconductor device that includes
 a fourth stacked region, wherein a fourth cell region including a fourth memory cell structure is on a fourth circuit region, and 
 a fourth non-stacked region, wherein a fourth pad region of the fourth circuit region is positioned outside the fourth stacked region, 
   wherein the first pad region is at a first corner portion adjacent to one side in a first direction and one side in a second direction that is transverse to the first direction in the first semiconductor device,   the second pad region is at a second corner portion adjacent to the one side in the first direction and the other side in the second direction in the second semiconductor device,   the third pad region is at a third corner portion adjacent to the other side in the first direction and the one side in the second direction in the third semiconductor device,   the fourth pad region is at a fourth corner portion adjacent to the other side in the first direction and the other side in the second direction in the fourth semiconductor device, and   the first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are electrically connected to each other by sequentially stacking the first pad region, the second pad region, the third pad region, and the fourth pad region.   
     
     
         20 . An electronic system, comprising:
 a main substrate;   a semiconductor device on the main substrate; and   a controller electrically connected to the semiconductor device on the main substrate,   wherein the semiconductor device includes a circuit region including a pad region, and a cell region including a memory cell structure on the circuit region, and   the semiconductor device includes a stacked region where the cell region is on the circuit region and a non-stacked region where the pad region of the circuit region is positioned outside the stacked region.