Frequency-division multiplexing

Abstract

A method is provided. In some examples, the method includes generating, by processing circuitry, a spread of chips representing an input bit. In addition, the method includes converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols. The method also includes mapping, by the processing circuitry, the pair of symbols to a single carrier signal and generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal. The method further includes transmitting, by the processing circuitry via an antenna, the RF signal.

What is claimed is: 
     
         1 . A non-transitory computer readable medium storing instructions that, when executed by processing circuitry, cause the processing circuitry to:
 obtain a bit;   produce a first spread bit and a second spread bit representing the bit, wherein a value of the first spread bit matching a value of the second spread bit indicates a first value of the bit and the value of the first spread bit not matching the value of the second spread bit indicates a second value of the bit;   produce a set of symbols responsive to the first spread bit and the second spread bit;   map the set of symbols to a single carrier signal to produce a mapped set of symbols;   produce a radio-frequency (RF) signal responsive to the single carrier signal including the mapped set of symbols; and   instruct an antenna to transmit the RF signal.   
     
     
         2 . The non-transitory computer readable medium of  claim 1 , wherein the first spread bit and the second spread bit are consecutive bits. 
     
     
         3 . The non-transitory computer readable medium of  claim 1 , wherein a first value of the first spread bit matching the second value of the second spread bit indicates a first value of the bit and the first value not matching the second value indicates a second value of the bit. 
     
     
         4 . The non-transitory computer readable medium of  claim 1 , wherein the bit is a first bit, the set of symbols is a first set of symbols, the single carrier signal is a first single carrier signal, wherein the instructions are further configured to cause the processing circuitry to:
 obtain a second bit;   produce a third spread bit and a fourth spread bit representing the second bit, wherein a value of the first spread bit matching a value of the second spread bit indicates a first value of the bit and the value of the first spread bit not matching the value of the second spread bit indicates aa second value of the bit; and   produce a second set of symbols responsive to the third spread bit and the fourth spread bit;   map the second set of symbols to a second single carrier signal to produce a mapped set of symbols, wherein the second single carrier signal is different from the first single carrier signal.   
     
     
         5 . The non-transitory computer readable medium of  claim 1 , wherein the instructions are further configured to cause the processing circuitry to add a cyclic prefix and a guard interval between the mapped set of symbols. 
     
     
         6 . The non-transitory computer readable medium of  claim 1 , wherein producing a set of symbols responsive to the first spread bit and the second spread bit comprising performing binary phase shift keying on the first spread bit and the second spread bit. 
     
     
         7 . The non-transitory computer readable medium of  claim 1 , wherein the instructions are further configured to cause the processing circuitry to produce a third spread bit and a fourth spread bit representing the bit. 
     
     
         8 . The non-transitory computer readable medium of  claim 1 , wherein the bit is a first bit, and the instructions are further configured to produce a third spread bit and a fourth spread bit responsive to obtaining a second bit, wherein a logical value of the second bit matches a logical value of the first bit, a logical value of the third spread bit is different than a logical value of the first spread bit and a logical value of the fourth spread bit is different than a logical value of the second spread bit. 
     
     
         9 . A system comprising:
 an antenna; and   processing circuitry coupled to the antenna, the processing circuitry configured to:
 receive, via the antenna, a radio frequency (RF) signal; 
 produce a frequency domain signal responsive to the RF signal; 
 produce a pair of spread bits responsive to a set of symbols of the frequency domain signal; and 
 determining a bit value responsive to the set of spread bits. 
   
     
     
         10 . The system of  claim 9 , wherein bits of the pair of spread bits are consecutive bits. 
     
     
         11 . The system of  claim 9 , wherein determining the bit value comprises determining the bit value to have a first value responsive to the set of spread bits matching and to a second value responsive to the set of spread bits not matching. 
     
     
         12 . The system of  claim 9 , wherein the set of spread bits is two spread bits. 
     
     
         13 . The system of  claim 9 , wherein the set of spread bits comprises four bits. 
     
     
         14 . The system of  claim 9 , wherein the set of symbols is a first symbol and a second symbol, wherein the second symbol and the first symbol have the same frequency. 
     
     
         15 . A non-transitory computer-readable medium storing instructions that, when executed by processing circuitry, cause the processing circuitry to:
 receive, via an antenna, a radio frequency (RF) signal;   produce a frequency domain signal responsive to the RF signal;   produce a pair of spread bits responsive to a pair of symbols of the frequency domain signal; and   determining a bid value responsive to the pair of spread bits.   
     
     
         16 . The non-transitory computer readable medium of  claim 15 , wherein bits of the pair of spread bits are consecutive bits. 
     
     
         17 . The non-transitory computer readable medium of  claim 15 , wherein determining the bit value comprises determining the bit value to have a first value responsive to the pair of spread bits matching and to a second value responsive to the pair of spread bits not matching. 
     
     
         18 . The non-transitory computer readable medium of  claim 15 , wherein the pair of spread bits is two spread bits. 
     
     
         19 . The non-transitory computer readable medium of  claim 15 , wherein the pair of spread bits comprises four bits. 
     
     
         20 . The non-transitory computer readable medium of  claim 15 , wherein the pair of symbols is a first symbol and a second symbol, wherein the second symbol and the first symbol have the same frequency.