Memory device with enhanced thermal conductivity

Abstract

Systems, apparatuses, and methods related to a memory device with enhanced thermal conductivity are described. Embodiments of the present technology can include thermal paths, such as material with a thermal conductivity value less than a threshold value, added into one or more layers in a memory device structure. The added material can provide a path for the thermal energy to dissipate from the memory device.

I/We claim: 
     
         1 . An apparatus comprising:
 a semiconductor substrate;   a memory cell over the semiconductor substrate;   a thermal path over the semiconductor substrate and separated from the memory cell along a lateral direction, the thermal path including thermally conductive and electrically insulative material; and   a dielectric material encompassing at least peripheral portions of the memory cell and the thermal path and forming a layer over the semiconductor substrate.   
     
     
         2 . The apparatus of  claim 1 ,
 wherein the thermal path includes material that is more thermally conductive than the dielectric material, and   wherein the thermal path is configured to transfer thermal energy out of or through the apparatus.   
     
     
         3 . The apparatus of  claim 1 , wherein the thermal path is electrically isolated, using the semiconductor substrate, from the memory cell. 
     
     
         4 . The apparatus of  claim 1 , wherein the thermally conductive and electrically insulative material is Aluminum Oxide or Aluminum Nitride. 
     
     
         5 . The apparatus of  claim 1 , wherein the thermal path includes a top portion, a bottom portion, or both that is exposed through the semiconductor substrate. 
     
     
         6 . A memory device comprising:
 a semiconductor substrate portion;   a dielectric layer over the semiconductor substrate portion;   at least one cell structure disposed in the dielectric layer and configured to store electrical charges representative of stored data; and   a thermal path located adjacent to the at least one cell structure and at least partially embedded in the dielectric layer, the thermal path including thermally conductive and electrically insulative material.   
     
     
         7 . The memory device of  claim 6 ,
 wherein the thermal path includes material that is more thermally conductive than dielectric material of the dielectric layer, and   wherein the thermal path is configured to transfer thermal energy out of or through the memory device.   
     
     
         8 . The memory device of  claim 6 , wherein the thermal path is electrically isolated, using the dielectric layer, from the at least one cell structure. 
     
     
         9 . The memory device of  claim 6 , wherein the thermally conductive and electrically insulative material is Aluminum Oxide or Aluminum Nitride. 
     
     
         10 . The memory device of  claim 6 , further comprising:
 active circuitry below the at least one cell structure and disposed on or above the semiconductor substrate portion; and   a through silicon via (TSV) extending along a vertical direction and through the dielectric layer, the semiconductor substrate portion, or both.   
     
     
         11 . The memory device of  claim 6 , further comprising:
 a logic device wafer including logic circuitry configured to facilitate storage, access, and maintenance of the data stored in the memory device,   wherein the semiconductor substrate portion, the dielectric layer, the at least one cell structure, and the thermal path comprise a semiconductor storage device configured to store data, the semiconductor storage device is wafer bonded to and over the logic device,   wherein the thermal path is configured to allow thermal energy generated by the logic device to travel upward and through the semiconductor storage device.   
     
     
         12 . The memory device of  claim 11 , wherein the semiconductor storage device is a first storage device having a first thermal path and directly attached to the logic device, the memory device further comprising:
 a second storage device having a second thermal path and wafer bonded directly to and over the first storage device, wherein the first and second thermal paths are aligned along a vertical line.   
     
     
         13 . The memory device of  claim 6 , wherein the memory device comprises a dynamic random-access memory (DRAM). 
     
     
         14 . A method comprising:
 providing a semiconductor substrate;   forming at least one cell structure over the semiconductor substrate, wherein the at least one cell structure is configured to store data;   forming a dielectric layer over the semiconductor substrate and encompassing the at least one cell structure;   forming, adjacent to the at least one cell structure, at least one isolated area based on removing a portion of the dielectric layer; and   forming a thermal path in the dielectric layer at the at least one isolated area by adding thermally conductive and electrically insulative material in the at least one isolated area.   
     
     
         15 . The method of  claim 14 , wherein forming the thermal path includes:
 spin coating to deposit the thermally conductive and electrically insulative material in the at least one isolated area of the dielectric layer.   
     
     
         16 . The method of  claim 14 , wherein forming the thermal path includes:
 a physical vapor deposition (PVD) process, a molybdenum (MO) process, a cut metal dielectric (CMD) process, or a combination thereof to deposit the thermally conductive and electrically insulative material.   
     
     
         17 . The method of  claim 14 , wherein the thermally conductive and electrically insulative material is added during a front-end-of-line (FEOL) layer manufacturing phase. 
     
     
         18 . The method of  claim 14 , wherein the thermally conductive and electrically insulative material is more thermally conductive than dielectric material of the dielectric layer, and wherein the thermally conductive and electrically insulative material provides the thermal path to transfer thermal energy out of or through the dielectric layer. 
     
     
         19 . The method of  claim 14 , further comprising:
 forming or attaching active circuitry on the semiconductor substrate, wherein the at least one cell structure is formed over the active circuitry; and   forming a thermal via or through silicon via (TSV) that extends through the dielectric layer and extends into the semiconductor substrate, wherein the thermal via or the TSV is located between the at least one cell structure and the thermal path,   wherein the thermal path is physically separated and electrically isolated, using the dielectric layer, from the thermal via or the TSV and the active circuitry.   
     
     
         20 . The method of  claim 14 , wherein forming the thermal path includes depositing Aluminum Oxide or Aluminum Nitride in the at least one isolated area.