Method for forming semiconductor device structure

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a first stacked nanostructure, and forming a first via adjacent to the first stacked nanostructure. The method includes forming a dummy gate structure over the first stacked nanostructure and the first via, and removing a portion of the first stacked nanostructure to form a trench. The method includes forming a first S/D structure in the trench, and a top surface of the first S/D structure is higher than a top surface of the first via. The method includes replacing the dummy gate structure with a gate structure, and the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer, and the gate electrode layer includes at least one metal layer. The method includes forming a first contact structure over the first S/D structure.

What is claimed is: 
     
         1 . A method for forming a semiconductor device structure, comprising:
 forming a first stacked nanostructure;   forming a first via adjacent to the first stacked nanostructure;   forming a dummy gate structure over the first stacked nanostructure and the first via;   removing a portion of the first stacked nanostructure to form a trench;   forming a first S/D structure in the trench, wherein a top surface of the first S/D structure is higher than a top surface of the first via;   replacing the dummy gate structure with a gate structure, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer over the gate dielectric layer, wherein the gate electrode layer comprises at least one metal layer,   forming a first contact structure over the first S/D structure; and   forming a second contact structure below the first S/D structure, wherein the first via is in direct contact with the first contact structure and the second contact structure.   
     
     
         2 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming an isolation material surrounding the first via.   
     
     
         3 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming a first interconnect structure over the first contact structure; and   forming a carrier wafer over the first interconnect structure.   
     
     
         4 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming a second via adjacent to the first stacked nanostructure, wherein the first via and the second via are on opposite sides of the first S/D structure; and   forming a sealing layer over the second via.   
     
     
         5 . The method for forming the semiconductor device structure as claimed in  claim 4 , further comprising:
 forming an isolation material surrounding the second via, wherein the isolation material is between the first S/D structure and the second via.   
     
     
         6 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming a sealing layer over the first via;   removing the sealing layer to expose the first via; and   forming the first contact structure over the first via.   
     
     
         7 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming a second via adjacent to the first stacked nanostructure, wherein the first via and the second via are on opposite sides of the first S/D structure, wherein the first contact structure is contact with the second via.   
     
     
         8 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein an entirety of the gate structure is higher than an entirety of the first via. 
     
     
         9 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 forming an etch stop layer over the first via and the first S/D structure; and   removing a portion of the etch stop layer to expose the first S/D structure.   
     
     
         10 . A method for forming a semiconductor device structure, comprising:
 forming a first stacked nanostructure;   forming a first via adjacent to the first stacked nanostructure;   forming a sealing layer on the first via;   forming a dummy gate structure over the first stacked nanostructure and the first via, wherein a bottom surface of the dummy gate structure is higher than a top surface of the first via;   removing a portion of the first stacked nanostructure to form a trench;   forming a first S/D structure in the trench;   removing the sealing layer to expose first via;   forming a silicide layer over the first S/D structure, wherein the silicide layer comprises a curved profile; and   forming a first contact structure over the first S/D structure, wherein the first contact structure is formed on a top surface and a sidewall surface of the first S/D structure.   
     
     
         11 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 forming a second contact structure below the first S/D structure, wherein the first via is in direct contact with the first contact structure and the second contact structure.   
     
     
         12 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 forming an etch stop layer over the first via and the first S/D structure;   forming a dielectric layer over the etch stop layer; and   removing a portion of the dielectric layer and a portion of the etch stop layer to expose the first S/D structure.   
     
     
         13 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 removing the dummy gate structure to form an opening; and   removing a portion of the first stacked nanostructure to form nanostructures.   
     
     
         14 . The method for forming the semiconductor device structure as claimed in  claim 13 , further comprising:
 forming a gate structure in the opening, wherein an entirety of the gate structure is higher than an entirety of the first via.   
     
     
         15 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 forming a gate spacer layer on a sidewall surface of the dummy gate structure, wherein a bottom surface of the gate spacer layer is higher than a bottom surface of the first contact structure.   
     
     
         16 . The method for forming the semiconductor device structure as claimed in  claim 10 , wherein a bottom surface of the gate spacer layer is higher than a top surface of the first via. 
     
     
         17 . A method for forming a semiconductor device structure, comprising:
 forming a first stacked nanostructure;   forming a first via adjacent to the first stacked nanostructure;   forming a dummy gate structure over the first stacked nanostructure and the first via;   forming a gate spacer layer on a sidewall surface of the dummy gate structure, wherein a bottom surface of the gate spacer layer is higher than a bottom surface of the first contact structure;   removing a portion of the first stacked nanostructure to form a trench;   forming a first S/D structure in the trench;   forming an etch stop layer over the first S/D structure, wherein the gate spacer layer is between the dummy gate structure and the etch stop layer; and   forming a first contact structure over the first S/D structure, wherein the first contact structure is formed on a top surface and a sidewall surface of the first S/D structure.   
     
     
         18 . The method for forming the semiconductor device structure as claimed in  claim 17 , further comprising:
 forming an isolation material surrounding the first via; and   forming an isolation structure surrounding the isolation material.   
     
     
         19 . The method for forming the semiconductor device structure as claimed in  claim 18 , further comprising:
 forming a second contact structure below the first S/D structure, wherein the isolation structure is between the second contact structure and the first via.   
     
     
         20 . The method for forming the semiconductor device structure as claimed in  claim 17 , further comprising:
 forming a second via adjacent to the first stacked nanostructure, wherein the first via and the second via are on opposite sides of the first S/D structure, wherein the first contact structure is contact with the second via.