Semiconductor device including vertical transistor and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first vertical transistor. The first vertical transistor includes a first channel region. The first vertical transistor further includes a first word line wrapping the first channel region. The first vertical transistor also includes a first word line dielectric layer between the first channel region and the first word line. The first vertical transistor furthermore includes a first conductive liner between the first word line dielectric layer and the first word line.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first vertical transistor, comprising:
 a first channel region; 
 a first word line surrounding the first channel region; 
 a first word line dielectric layer surrounding the first word line; and 
 a first conductive liner surrounding the first word line; 
   a first barrier layer on sidewalls of the first word line and directly contacting the first conductive liner; and   a second vertical transistor adjacent to the first vertical transistor;   wherein the first barrier layer has a non-uniform width.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first barrier layer comprises a first portion contacting the first conductive liner and a second portion contacting the first word line. 
     
     
         3 . The semiconductor device of  claim 2 , wherein a width of the first portion of the first barrier layer is less than a width of the second portion of the first barrier layer. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first conductive liner is partially protruded into the first barrier layer. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first conductive liner is partially integrally formed with the first barrier layer. 
     
     
         6 . The semiconductor device of  claim 4 , wherein the first conductive liner is partially protruded from an edge of the first barrier layer. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the first conductive liner is partially integrally formed with the first barrier layer. 
     
     
         8 . The semiconductor device of  claim 6 , further comprising a dielectric layer encapsulating the first vertical transistor, wherein the dielectric layer directly contacts the first conductive liner and the first barrier layer. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the second vertical transistor comprises:
 a second channel region;   a second word line surrounding the first channel region;   a second word line dielectric layer surrounding the first word line; and   a second conductive liner surrounding the first word line; and   a second barrier layer on sidewalls of the second word line and directly contacting the second conductive liner.   
     
     
         10 . A method of manufacturing a semiconductor device, comprising:
 providing a capacitor over a substrate; and   forming a vertical transistor over the capacitor, wherein the vertical transistor comprises:
 a channel region; 
 a word line wrapping the channel region; 
 a word line dielectric layer between the channel region and the word line; and 
 a conductive liner between the word line dielectric layer and the word line. 
   
     
     
         11 . The method of  claim 10 , wherein forming the vertical transistor comprises:
 forming a trench over the capacitor;   forming a word line material in the trench;   etching the word line material to form the word line and an opening encircled by the word line; and   forming the conductive liner in the opening.   
     
     
         12 . The method of  claim 11 , wherein forming the vertical transistor further comprises:
 forming a barrier layer on sidewalls of the trench prior to forming the word line material; and   etching the barrier layer to form the opening encircled by the word line.   
     
     
         13 . The method of  claim 12 , wherein etching the word line material and etching the barrier layer are performed in a same operation. 
     
     
         14 . The method of  claim 11 , wherein forming the conductive liner comprises:
 forming a conductive liner material in the opening; and   etching the conductive liner material to form the conductive liner and a through hole encircled by the conductive liner.   
     
     
         15 . The method of  claim 11 , wherein forming the vertical transistor further comprises:
 forming the word line dielectric layer on the conductive liner.   
     
     
         16 . The method of  claim 15 , wherein forming the word line dielectric layer comprises:
 forming a word line dielectric material in a first through hole encircled by the conductive liner; and   etching the word line dielectric material to form the word line dielectric layer and a second through hole encircled by the word line dielectric layer.   
     
     
         17 . The method of  claim 16 , wherein forming the vertical transistor further comprises:
 forming the channel region in the second through hole.   
     
     
         18 . The method of  claim 10 , further comprising:
 forming a dielectric layer over the capacitor, wherein the dielectric layer defines a trench over the capacitor, and the vertical transistor is formed in the trench.   
     
     
         19 . The method of  claim 10 , further comprising:
 forming a bit line over the vertical transistor.