Neuromorphic memory device and neuromorphic system using the same
Abstract
The present disclosure relates to a neuromorphic memory device and a neuromorphic system using the same. The neuromorphic memory device includes a three-dimensional memory element including NAND cell strings, a bit line that outputs an output signal, forms a first axis of the three-dimensional memory element, and connects NAND cells existing on the same first axis among the NAND cell strings, a word line that receives an input signal, forms a second axis of the three-dimensional memory element, and connects NAND cells existing on the same second axis among the NAND cell strings, and a string selection line that forms a layer of an artificial intelligence neural network, forms a third axis of the three-dimensional memory element, and connects NAND cells existing on the same third axis among the NAND cell strings by intersecting the bit line and the word line.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A neuromorphic memory device comprising:
a three-dimensional memory element including a plurality of NAND cell strings; a bit line that outputs an output signal, forms a first axis of the three-dimensional memory element, and connects NAND cells existing on the same first axis among the plurality of NAND cell strings; a word line that receives an input signal, forms a second axis of the three-dimensional memory element, and connects NAND cells existing on the same second axis among the plurality of NAND cell strings; and a string selection line that forms a layer of an artificial intelligence neural network, forms a third axis of the three-dimensional memory element, and connects NAND cells existing on the same third axis among the plurality of NAND cell strings by intersecting the bit line and the word line.
2 . The neuromorphic memory device of claim 1 , wherein when the number of inputs of the artificial intelligence neural network is greater than the number of word lines, the neuromorphic memory device configures the artificial intelligence neural network by configuring a network topology with the string selection lines.
3 . The neuromorphic memory device of claim 2 , wherein the neuromorphic memory device configures the network topology by bundling a plurality of adjacent string selection lines.
4 . The neuromorphic memory device of claim 1 , wherein the neuromorphic memory device configures the number of bit lines to be the same as the number of outputs of the artificial intelligence neural network.
5 . The neuromorphic memory device of claim 1 , wherein the neuromorphic memory device sequentially arranges the layers of the artificial intelligence neural network according to the increase in the string selection lines.
6 . The neuromorphic memory device of claim 1 , wherein the neuromorphic memory device implements a synapse of the artificial intelligence neural network through the NAND cells and stores weights in the NAND cells.
7 . The neuromorphic memory device of claim 1 , wherein the neuromorphic memory device performs a read operation of the artificial intelligence neural network only through a word line connected to the input signal when sparsity of the input signal is detected.
8 . The neuromorphic memory device of claim 1 , wherein the neuromorphic memory device reads weight of the NAND cell by operating the bit line in a manner in which output currents are summed over time (temporal-sum).
9 . A neuromorphic system comprising:
a neuromorphic memory device; and a neuromorphic computational device that processes input spikes and output spikes input and output through the neuromorphic memory device, wherein the neuromorphic memory device uses a neuromorphic memory including a three-dimensional memory device that includes a NAND cell layer arranged along a first axis and a plurality of NAND cell strings each including a plurality of NAND cells arranged along a second axis within the NAND cell layer, and arranges the NAND cell layer along a third axis, a bit line that outputs the output spike, forms the first axis of the three-dimensional memory device, and connects NAND cells existing along the same first axis among the plurality of NAND cell strings, a word line that receives the input spike, forms the second axis of the three-dimensional memory device, and connects NAND cells existing along the same second axis among the plurality of NAND cell strings, and a string selection line that forms a layer of an artificial intelligence neural network, forms the third axis of the three-dimensional memory element, and connects NAND cells existing on the same third axis among the plurality of NAND cell strings by intersecting the bit line and the word line.
10 . The neuromorphic system of claim 9 , wherein the artificial intelligence neural network is a spiking neural network (SNN).
11 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device configures the artificial intelligence neural network by configuring a network topology with the string selection line when the number of inputs of the artificial intelligence neural network is greater than the number of word lines.
12 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device configures the number of bit lines so that the number of outputs of the artificial intelligence neural network is the same.
13 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device sequentially arranges layers of the artificial intelligence neural network according to an increase in the string selection line.
14 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device implements synapses of the artificial intelligence neural network through the NAND cells and stores weights in the NAND cells.
15 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device performs a read operation of the artificial intelligence neural network only through a word line connected to the input spike when sparsity of the input spike is detected.
16 . The neuromorphic system of claim 9 , wherein the neuromorphic memory device reads weight of the NAND cell by operating the bit line in a manner in which output currents are summed over time (temporal-sum).Join the waitlist — get patent alerts
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