Semiconductor package

Abstract

A semiconductor package includes: a substrate; first semiconductor chips mounted on the substrate; a second semiconductor chip mounted on the substrate; a first molding member covering sides of the first semiconductor chips; and a second molding member covering the first semiconductor chips and the second semiconductor chip. Each of the first semiconductor chip includes a plurality of semiconductor chips that are stacked on each other along a first direction. The first molding member includes recesses extending along the first direction. The recesses include first portions, which extend to edges of the first molding member and have a first width, and second portions, which are connected to the first portions and are positioned more inward into the first molding member than the first portions. The second portions have a second width that is greater than the first width, and the second molding member fills at least parts of the recesses.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a substrate;   first semiconductor chips mounted on the substrate;   a second semiconductor chip mounted on the substrate and spaced apart from the first semiconductor chips;   a first molding member covering sides of each of the first semiconductor chips; and   a second molding member covering the first semiconductor chips and the second semiconductor chip, and disposed on the substrate,   wherein   each of the first semiconductor chip includes a plurality of semiconductor chips that are stacked on each other along a first direction,   the first molding member includes recesses, which are formed to extend along the first direction,   the recesses include first portions, which extend to edges of the first molding member and have a first width, and second portions, which are connected to the first portions and are positioned more inward into the first molding member than the first portions,   the second portions have a second width that is greater than the first width, and   the second molding member fills at least parts of the recesses.   
     
     
         2 . The semiconductor package of  claim 1 , wherein
 the first width of the first portions is substantially constant along the first direction, and   the second width of the second portions is substantially constant along the first direction.   
     
     
         3 . The semiconductor package of  claim 2 , wherein
 bottom surfaces of the recesses are spaced apart from a bottom surface of the second molding member.   
     
     
         4 . The semiconductor package of  claim 1 , wherein the recesses have first areas and second areas, which are formed on the first areas, and include first recesses and second recesses, wherein the first recesses are formed in the first areas and include the first portions, which have the first width, and the second portions, which have the second width, wherein the second recesses are formed in the second areas and include third portions and fourth portions, wherein the third portions have a third width and extend to edges of the first molding member, and wherein the fourth portions are connected to the third portions and have a fourth width that is greater than the third width. 
     
     
         5 . The semiconductor package of  claim 4 , wherein
 the third width is greater than the first width, and   the fourth width is greater than the second width.   
     
     
         6 . The semiconductor package of  claim 5 , wherein in the recesses where the first and second molding members contact each other, side portions of the first molding member have a stair-like shape. 
     
     
         7 . The semiconductor package of  claim 5 , wherein relative to the sides of each of the first semiconductor chips, first sides of the first molding member in the first areas protrude in a second direction beyond second sides of the first molding member in the second areas, wherein the second direction intersects the first direction. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the second molding member, filling the first portions and the second portions of the recesses, has a T shape. 
     
     
         9 . The semiconductor package of  claim 7 , wherein the first molding member anchors the second molding member that fills the first portions and the second portions of the recesses. 
     
     
         10 . The semiconductor package of  claim 1 , wherein
 the first semiconductor chips are memory chips, and   the second semiconductor chip is a logic chip.   
     
     
         11 . A semiconductor package comprising:
 an interposer structure;   first semiconductor chips mounted on the interposer structure and including a stack of a plurality of semiconductor chips;   a plurality of first bumps electrically connecting the interposer structure to the first semiconductor chips and disposed between the interposer structure and the first semiconductor chips;   a first molding member at least partially surrounding the first semiconductor chips and including a plurality of recesses, which are formed in a stacking direction of the plurality of semiconductor chips; and   a second molding member covering the first semiconductor chips and disposed on the interposer structure,   wherein   the recesses have first areas and second areas, which are formed on the first areas, and include first recesses and second recesses, wherein the first recesses are formed in the first areas and include first portions, which have a first width, and second portions, which have a second width that is greater than the first width, wherein the second recesses are formed in the second areas and include third portions, which have a third width, and fourth portions, which have a fourth width that is greater than the third width, and   the second molding member fills the first recesses and the second recesses.   
     
     
         12 . The semiconductor package of  claim 11 , wherein
 the third width is greater than the first width, and   the fourth width is greater than the second width.   
     
     
         13 . The semiconductor package of  claim 11 , wherein the second molding member, which fills the first recesses and the second recesses, has a T shape. 
     
     
         14 . The semiconductor package of  claim 13 , wherein the first molding member anchors the second molding member that fills the first portions, the second portions, the third portions, and the fourth portions. 
     
     
         15 . The semiconductor package of  claim 12 , wherein in the recesses where the first and second molding members contact each other, side portions of the first molding member have a stair-like shape. 
     
     
         16 . The semiconductor package of  claim 11 , wherein a first length from sides of each of the first semiconductor chips to first sides of the first molding member in the first areas is greater than a second length from the sides of each of the first semiconductor chips to second sides of the first molding member in the second areas. 
     
     
         17 . The semiconductor package of  claim 11 , further comprising:
 a second semiconductor chip spaced apart from the first semiconductor chips and mounted on the interposer structure;   a plurality of second bumps electrically connecting the interposer structure to the second semiconductor chip; and   an underfill filling gaps between the interposer structure and the first semiconductor chips and between the interposer structure and the second semiconductor chip and covering the plurality of first bumps and the plurality of second bumps.   
     
     
         18 . The semiconductor package of  claim 17 , further comprising:
 a circuit board on which the interposer structure is disposed;   first solder balls electrically connecting the interposer structure to the circuit board; and   a stiffener spaced apart from the interposer structure and disposed on the circuit board,   wherein the interposer structure includes an interposer, an interlayer insulating layer, which is disposed on the interposer, through vias, which penetrate the interposer, and redistribution layers, which are formed in the interlayer insulating layer.   
     
     
         19 . The semiconductor package of  claim 18 , wherein
 the first semiconductor chips are memory chips, and   the second semiconductor chip is a logic chip.   
     
     
         20 . A semiconductor package comprising:
 a circuit board;   an interposer structure disposed on the circuit board;   first solder balls electrically connecting the interposer structure to the circuit board;   memory chips mounted on the interposer structure and including a stack of a plurality of semiconductor chips;   a logic chip spaced apart from the memory chips and mounted on the interposer structure;   a plurality of first bumps electrically connecting the interposer structure to the memory chips, and electrically connecting the interposer structure to the logic chip, wherein the plurality of first bumps are disposed between the interposer structure and the memory chips and between the interposer structure and the logic chip;   a first molding member at least partially surrounding the memory chips and including a plurality of recesses, which extend in a first direction; and   a second molding member covering the memory chips and the logic chip, and covering the first molding member,   wherein   the recesses include first recesses, which are formed in first areas, and second recesses, which are formed in second areas that are formed on the first areas,   the first recesses include first portions, which have a first width, and second portions, which have a second width that is greater than the first width,   the second recesses include third portions, which have a third width, and fourth portions, which have a fourth width that is greater than the third width,   the third width is greater than the first width,   the fourth width is greater than the second width,   the second molding member fills the first recesses and the second recesses and has a T shape, and   in the recesses, sides of the first molding member have a stair-like shape.