Bitline sensing amplifier and memory device including the same

Abstract

Disclosed is a BLSA that reads data of a memory cell and includes an amplifying circuit amplifying a difference between a first voltage level of the second node and a second voltage level of the first node. The amplifying circuit includes a first PMOS transistor connected between the second node and a third node and operating in response to the second voltage level, a second PMOS transistor connected between the first node and the third node and operating in response to the first voltage level, a first NMOS transistor connected between the second node and a fourth node connected to a first bitline of a first memory cell and operating in response to the first voltage level, and a second NMOS transistor connected between the second node and a fifth node connected to a second bitline of a second memory cell and operating in response to the second voltage level.

What is claimed is: 
     
         1 . A bitline sensing amplifier configured to read data of a memory cell, the bitline sensing amplifier comprising:
 an equalization circuit connected to a first node and a second node, the equalization circuit configured to provide an equalization voltage to the first node and the second node; and   an amplifying circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node, the amplifying circuit comprising:   a first p-type metal-oxide-semiconductor (PMOS) transistor connected between the second node and a third node, the first PMOS transistor configured to operate in response to the second voltage level;   a second PMOS transistor connected between the first node and the third node, the second PMOS transistor configured to operate in response to the first voltage level;   a first n-type metal-oxide-semiconductor (NMOS) transistor connected between the second node and a fourth node connected to a first bitline of a first memory cell, the first NMOS transistor configured to operate in response to the first voltage level; and   a second NMOS transistor connected between the second node and a fifth node connected to a second bitline of a second memory cell, the second NMOS transistor configured to operate in response to the second voltage level.   
     
     
         2 . The bitline sensing amplifier of  claim 1 , further comprising:
 a first read/write circuit connected to the second node and the fifth node;   a second read/write circuit connected to the first node and the fourth node, wherein the first read/write circuit is provided with first read data of the first memory cell through the second node and provides second write data to be written in the second memory cell through the fifth node, and   wherein the second read/write circuit is provided with second read data of the second memory cell through the first node and provides first write data to be written in the first memory cell through the fourth node.   
     
     
         3 . The bitline sensing amplifier of  claim 1 , wherein the equalization circuit includes:
 a first transistor connected between the first node and an equalization node to which the equalization voltage is applied, the first transistor configured to operate in response to an equalization signal; and   a second transistor connected between the equalization node and the second node, the second transistor configured to operate in response to the equalization signal.   
     
     
         4 . The bitline sensing amplifier of  claim 1 , wherein the equalization circuit includes:
 a first transistor connected between the first node and an equalization node to which the equalization voltage is applied, the first transistor configured to operate in response to an equalization signal; and   a second transistor connected between the first node and the second node, the second transistor configured to operate in response to the equalization signal.   
     
     
         5 . The bitline sensing amplifier of  claim 2 , wherein the first read/write circuit includes:
 an input/output circuit configured to receive the first read data and to provide the second write data;   a first transistor connected between the second node and the input/output circuit, the first transistor configured to operate in response to a read enable signal; and   a second transistor connected between the second node and the fifth node, the second transistor configured to operate in response to a write enable signal.   
     
     
         6 . The bitline sensing amplifier of  claim 2 , wherein the first read/write circuit includes:
 an input/output circuit configured to receive the first read data and to provide the second write data;   a first transistor connected between the second node and the input/output circuit, the first transistor configured to operate in response to a read enable signal; and   a second transistor connected between the fifth node and the input/output circuit, the second transistor configured to operate in response to a write enable signal.   
     
     
         7 . The bitline sensing amplifier of  claim 2 , wherein the equalization circuit performs a precharge operation of providing the equalization voltage to the first node and the second node,
 wherein a voltage level of the fourth node has a value obtained by subtracting a threshold voltage level of the first NMOS transistor from the equalization voltage in response to the precharge operation, and   wherein a voltage level of the fifth node has a value obtained by subtracting a threshold voltage level of the second NMOS transistor from the equalization voltage in response to the precharge operation.   
     
     
         8 . The bitline sensing amplifier of  claim 7 , wherein the third node is connected to a power NMOS transistor, and
 wherein the power NMOS transistor is connected to the third node and a power node to which a power supply voltage is applied and is configured to operate in response to a control signal.   
     
     
         9 . The bitline sensing amplifier of  claim 8 , wherein the second memory cell is a reference cell storing reference data, and
 wherein, in response to that wordlines of the first memory cell and the second memory cell are activated,   a first current corresponding to first data of the first memory cell flows through the first node and the fourth node, and   a second current corresponding the reference data of the second memory cell flows through the second node and the fifth node, and   wherein, when data 1 is stored in the first memory cell, the first current is larger than the second current.   
     
     
         10 . The bitline sensing amplifier of  claim 9 , wherein the second voltage level decreases in response to the first current,
 wherein the first voltage level decreases in response to the second current, and   wherein, when the data 1 is stored in the first memory cell, in response to that the second voltage level decreases to be faster than the first voltage level, the second NMOS transistor is turned off, and the second voltage level is clamped.   
     
     
         11 . The bitline sensing amplifier of  claim 10 , wherein the power NMOS transistor is turned on through the control signal, and
 wherein, when the power supply voltage is provided to the third node, the amplifying circuit starts to amplify the difference between the first voltage level and the second voltage level.   
     
     
         12 . The bitline sensing amplifier of  claim 11 , wherein, when the data 1 is stored in the first memory cell, the amplifying circuit amplifies the first voltage level so as to reach the equalization voltage. 
     
     
         13 . A bitline sensing amplifier configured to read data of a memory cell, the bitline sensing amplifier comprising:
 an equalization circuit connected to a first node and a second node, the equalization circuit configured to provide an equalization voltage to the first node and the second node;   a first amplifying circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node; and   a second amplifying circuit configured to disconnect the bitline sensing amplifier from a first bitline connected to a first memory cell and a second bitline connected to a second memory cell,   wherein the first amplifying circuit comprises:   a first n-type metal-oxide-semiconductor (NMOS) transistor connected between the first node and a third node, the first NMOS transistor configured to operate in response to the first voltage level; and   a second NMOS transistor connected between the second node and a fourth node, the second NMOS transistor configured to operate in response to the second voltage level, and   wherein the second amplifying circuit comprises:   a third NMOS transistor connected between a fifth node connected to the third node and the first bitline, the third NMOS transistor configured to operate in response to a first control signal; and   a fourth NMOS transistor connected between a sixth node connected to the fourth node and the second bitline, the fourth NMOS transistor configured to operate in response to the first control signal.   
     
     
         14 . The bitline sensing amplifier of  claim 13 , wherein the first amplifying circuit further includes:
 a fifth NMOS transistor connected between a power node to which a power supply voltage is applied and a seventh node, the fifth NMOS transistor configured to operate in response to a second control signal;   a first PMOS transistor connected between the second node and the seventh node, the first PMOS transistor configured to operate in response to the second voltage level; and   a second PMOS transistor connected between the first node and the seventh node, the second PMOS transistor configured to operate in response to the first voltage level.   
     
     
         15 . The bitline sensing amplifier of  claim 14 , wherein the second amplifying circuit further includes:
 a sixth NMOS transistor connected between a ground node and an eighth node, the sixth NMOS transistor configured to operate in response to the second control signal;   a seventh NMOS transistor connected between the fifth node and the eighth node, the seventh NMOS transistor configured to operate in response to the second control signal; and   an eighth NMOS transistor connected between the sixth node and the eighth node, the eight NMOS transistor configured to operate in response to the second control signal, and   wherein the first control signal and the second control signal are complementary signals.   
     
     
         16 . The bitline sensing amplifier of  claim 15 , further comprising:
 a first read/write circuit connected to the second node and the fourth node; and   a second read/write circuit connected to the first node and the third node,   wherein the first read/write circuit is provided with first read data of the first memory cell through the second node and provides second write data to be written in the second memory cell through the fourth node, and   wherein the second read/write circuit is provided with second read data of the second memory cell through the first node and provides first write data to be written in the first memory cell through the third node.   
     
     
         17 . The bitline sensing amplifier of  claim 15 , wherein the equalization circuit includes:
 a first transistor connected between the first node and an equalization node to which the equalization voltage is applied, the first transistor configured to operate in response to an equalization signal; and   a second transistor connected between the equalization node and the second node, the second transistor configured to operate in response to the equalization signal.   
     
     
         18 . The bitline sensing amplifier of  claim 15 , wherein the equalization circuit includes:
 a first transistor connected between the first node and an equalization node to which the equalization voltage is applied, the first transistor configured to operate in response to an equalization signal; and   a second transistor connected between the first node and the second node, the second transistor configured to operate in response to the equalization signal.   
     
     
         19 . The bitline sensing amplifier of  claim 15 , wherein the first amplifying circuit amplifies the difference between the first voltage level and the second voltage level in response to the second control signal, and
 wherein, in response to the first control signal, the second amplifying circuit disconnects the first bitline and the fifth node and disconnects the second bitline and the sixth node.   
     
     
         20 . A memory device configured to store data, the memory device comprising:
 a memory cell array configured to store the data and including a first memory cell, a second memory cell, and a bitline sensing amplifier; and   an input/output circuit configured to input or receive the data to or from the memory cell array,   wherein the bitline sensing amplifier includes:   an equalization circuit connected to a first node and a second node, the equalization circuit configured to provide an equalization voltage to the first node and the second node; and   an amplifying circuit configured to amplify a difference between a first voltage level of the second node and a second voltage level of the first node, and   wherein the amplifying circuit includes:   a first NMOS transistor connected between the first node and a third node connected to a first bitline of the first memory cell, the first NMOS transistor configured to operate in response to the first voltage level; and   a second NMOS transistor connected between the second node and a fourth node connected to a second bitline of the second memory cell, the second NMOS transistor configured to operate in response to the second voltage level.