Generative Artificial Intelligence-Based Random Test Generation Framework For Processor Verification

Abstract

Techniques pertaining to generative artificial intelligence (GAI)-based random test generation framework for processor verification are described. An apparatus generates one of more random test cases with an aid of a GAI-assisted random verification program (GRVP) framework. The apparatus also performs validation testing on a design of a processor using the one or more random test cases.

What is claimed is: 
     
         1 . A method, comprising:
 generating, by a processor of an apparatus, one or more random test cases with an aid of a generative artificial intelligence (GAI)-assisted random verification program (GRVP) framework; and   performing, by the processor, validation testing on a design of a processor using the one or more random test cases.   
     
     
         2 . The method of  claim 1 , wherein the generating of the one or more random test cases comprises utilizing a retrieval augmented generator (RAG) in the GRVP framework to perform operations comprising:
 receiving a template-based user input along with one or more random feature specifications;   receiving one or more application programming interfaces (APIs);   learning from documents and examples; and   prompting with an aid of relevant chunks shared to a large language model (LLM) in the GRVP framework.   
     
     
         3 . The method of  claim 2 , wherein the generating of the one or more random test cases further comprises:
 utilizing the LLM to generate one or more test cases along with documentation based on an input received from the RAG; and   generating the one or more random test cases in a predefined language based on the one or more test cases generated by the LLM.   
     
     
         4 . The method of  claim 2 , wherein the utilizing of the RAG further comprises utilizing the RAG to perform operations comprising:
 utilizing the LLM to generate one or more test cases along with documentation based on an input received from the RAG;   integrating reference libraries; and   learning examples with the APIs to enhance generation of random test programs.   
     
     
         5 . The method of  claim 2 , wherein the generating of the one or more random test cases further comprises utilizing a C or C++-based random verification program (CRVP) generator to generate the one or more APIs. 
     
     
         6 . The method of  claim 5 , wherein the generating of the one or more random test cases further comprises utilizing the CRVP generator to generate one or more random verification programs in C that are used in validating the design of the processor. 
     
     
         7 . The method of  claim 6 , wherein the one or more C-random verification programs are instruction set architecture (ISA)-independent. 
     
     
         8 . The method of  claim 6 , wherein the utilizing of the CRVP generator to generate one or more C-random verification programs comprises utilizing the CRVP generator to perform operations comprising:
 running application and operating system (OS) fragments on simulators;   collecting snapshots of input and output registers and control and status registers (CSRs);   creating random expressions of an order of 3 or 4; and   calculating outputs using known values as inputs.   
     
     
         9 . The method of  claim 2 , wherein the generating of the one or more random test cases further comprises utilizing a Python-based random verification program (PyRVP) generator to generate the one or more APIs. 
     
     
         10 . The method of  claim 9 , wherein the generating of the one or more random test cases further comprises utilizing the PyRVP generator to generate one or more random verification programs in Assembly that are used in validating the design of the processor. 
     
     
         11 . An apparatus, comprising:
 a memory configured to store information, data and instructions; and   a processor coupled to the memory and configured to perform operations comprising:   generating one of more random test cases with an aid of a generative artificial intelligence (GAI)-assisted random verification program (GRVP) framework; and   performing validation testing on a design of a processor using the one or more random test cases.   
     
     
         12 . The apparatus of  claim 11 , wherein the generating of the one or more random test cases comprises utilizing a retrieval augmented generator (RAG) in the GRVP framework to perform operations comprising:
 receiving a template-based user input along with one or more random feature specifications;   receiving one or more application programming interfaces (APIs);   learning from documents and examples; and   prompting with an aid of relevant chunks shared to a large language model (LLM) in the GRVP framework.   
     
     
         13 . The apparatus of  claim 12 , wherein the generating of the one or more random test cases further comprises:
 utilizing the LLM to generate one or more test cases along with documentation based on an input received from the RAG; and   generating the one or more random test cases in a predefined language based on the one or more test cases generated by the LLM.   
     
     
         14 . The apparatus of  claim 12 , wherein the utilizing of the RAG further comprises utilizing the RAG to perform operations comprising:
 utilizing the LLM to generate one or more test cases along with documentation based on an input received from the RAG;   integrating reference libraries; and   learning examples with the APIs to enhance generation of random test programs.   
     
     
         15 . The apparatus of  claim 12 , wherein the generating of the one or more random test cases further comprises utilizing a C or C++-based random verification program (CRVP) generator to generate the one or more APIs. 
     
     
         16 . The apparatus of  claim 15 , wherein the generating of the one or more random test cases further comprises utilizing the CRVP generator to generate one or more random verification programs in C that are used in validating the design of the processor. 
     
     
         17 . The apparatus of  claim 16 , wherein the one or more C-random verification programs are instruction set architecture (ISA)-independent. 
     
     
         18 . The apparatus of  claim 16 , wherein the utilizing of the CRVP generator to generate one or more C-random verification programs comprises utilizing the CRVP generator to perform operations comprising:
 running application and operating system (OS) fragments on simulators;   collecting snapshots of input and output registers and control and status registers (CSRs);   creating random expressions of an order of 3 or 4; and   calculating outputs using known values as inputs.   
     
     
         19 . The apparatus of  claim 12 , wherein the generating of the one or more random test cases further comprises utilizing a Python-based random verification program (PyRVP) generator to generate the one or more APIs. 
     
     
         20 . The apparatus of  claim 19 , wherein the generating of the one or more random test cases further comprises utilizing the PyRVP generator to generate one or more random verification programs in Assembly that are used in validating the design of the processor.