Semiconductor device including a memory cell having a carrier tunneling layer

Abstract

A semiconductor device includes a lower interconnection line; a memory cell structure over the lower interconnection line; and an upper interconnection line over the memory cell structure. The memory cell structure includes a first electrode; a selection element over the first electrode; a first carrier tunneling layer over the selection element layer; a second electrode over the first carrier tunneling layer; a memory element layer over the second electrode; and a third electrode over the memory element layer. The first carrier tunneling layer includes an insulating layer doped with at least one pentavalent element.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first interconnection line;   a memory cell structure structured disposed over the first interconnection line; and   a second interconnection line disposed over the memory cell structure,   wherein the memory cell structure includes:   a first electrode disposed over the first interconnection line;   a selection element layer disposed over the first electrode;   a first carrier tunneling layer disposed over the selection element layer;   a middle electrode disposed over the first carrier tunneling layer;   a memory element layer disposed over the middle electrode; and   a second electrode disposed over the memory element layer,   wherein the first carrier tunneling layer includes an insulating layer doped with at least one pentavalent element.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein the first carrier tunneling layer includes a silicon-based insulating layer doped with arsenic.   
     
     
         3 . The semiconductor device of  claim 2 ,
 wherein the silicon-based insulating layer doped with arsenic includes at least one of oxygen or nitrogen.   
     
     
         4 . The semiconductor device of  claim 3 ,
 wherein the silicon-based insulating layer doped with arsenic further includes at least one of boron, carbon, or hydrogen.   
     
     
         5 . The semiconductor device of  claim 1 ,
 wherein a thickness of the first carrier tunneling layer is a range of 3 Å to 50 Å.   
     
     
         6 . The semiconductor device of  claim 1 ,
 wherein the first carrier tunneling layer includes a metal oxide layer doped with arsenic.   
     
     
         7 . The semiconductor device of  claim 6 ,
 wherein the metal oxide layer includes at least one of a tungsten oxide layer, a titanium oxide layer, a tantalum oxide layer, an aluminum oxide layer, a copper oxide layer, a zinc oxide layer, a nickel oxide layer, a cobalt oxide layer, a chromium oxide layer, a niobium oxide layer, a molybdenum oxide layer, a ruthenium oxide layer, a magnesium oxide layer, a hafnium oxide layer, or a zirconium oxide layer.   
     
     
         8 . The semiconductor device of  claim 1 ,
 wherein the selection element layer includes a silicon oxide doped with arsenic.   
     
     
         9 . The semiconductor device of  claim 1 ,
 wherein the selection element layer includes a carbon-based material layer.   
     
     
         10 . The semiconductor device of  claim 9 ,
 wherein the selection element layer further includes at least one of hydrogen, nitrogen, or oxygen.   
     
     
         11 . The semiconductor device of  claim 9 ,
 wherein the selection element layer further includes at least one of boron, aluminum, gallium, indium, or thallium.   
     
     
         12 . The semiconductor device of  claim 9 ,
 wherein the selection element layer further includes at least one of arsenic, phosphorus, or antimony.   
     
     
         13 . The semiconductor device of  claim 1 ,
 wherein the memory cell structure further includes a second carrier tunneling layer located between the first electrode and the selection element layer.   
     
     
         14 . The semiconductor device of  claim 1 ,
 wherein the middle electrode includes a carbon-based material layer.   
     
     
         15 . A semiconductor device comprising:
 a lower interconnection line;   a first electrode disposed over the lower interconnection line;   a selection element layer disposed over the first electrode;   a second electrode disposed over the selection element layer;   a memory element layer disposed over the second electrode;   a third electrode disposed over the memory element layer;   an upper interconnection line disposed on the third electrode; and   a carrier tunneling layer disposed between the first electrode and the selection element layer or between the selection element layer and the second electrode,   wherein the second electrode includes a carbon-based material layer, and   wherein the carrier tunneling layer includes an insulating layer doped with at least one pentavalent element.   
     
     
         16 . The semiconductor device of  claim 15 ,
 wherein the selection element layer includes a silicon oxide layer doped with arsenic.   
     
     
         17 . The semiconductor device of  claim 15 ,
 wherein the carbon-based material layer includes:   carbon;   at least one of hydrogen, nitrogen, or oxygen; and   at least one of arsenic, phosphorus, or antimony.   
     
     
         18 . The semiconductor device of  claim 17 ,
 wherein the carbon-based material layer further includes at least one of boron, aluminum, gallium, indium, or thallium.   
     
     
         19 . The semiconductor device of  claim 15 ,
 wherein the carrier tunneling layer includes a silicon-based insulating layer doped with arsenic.   
     
     
         20 . The semiconductor device of  claim 15 ,
 wherein the carrier tunneling layer includes a metal oxide layer doped with arsenic.