Apparatus and methods for embedding deep trench capacitor (dtc) components in a substrate

Abstract

Apparatus and methods for embedding deep trench capacitors (DTCs) in a package substrate. The method includes fabricating an integrated circuit on a silicon substrate core and identifying a deep trench capacitor (DTC) component to integrate with the integrated circuit. A cavity is created in the silicon substrate core to accommodate the DTC component. The cavity extends therethrough, like a through-hole. A temporary carrier is attached to the silicon substrate to create a cavity floor. A gap magnitude is determined, which is a difference between the thickness of the silicon substrate core and the thickness of the DTC component. An epoxy material with a minimum bond line that matches the gap magnitude is selected and implemented to fill the gap in fabrication. The minimum bond line is controlled by selection of particles to use in the epoxy material.

What is claimed is: 
     
         1 . A device, comprising:
 a first substrate having an upper surface, a lower surface, and a first thickness;   a capacitor component in the first substrate, the capacitor component comprising a second substrate and a second thickness that is less than the first thickness, the capacitor component comprises a trench formed in the second substrate that extends orthogonally downward from the upper surface with an aspect ratio of at least 10, wherein the capacitor component comprises metal layers that conformally follow the trench; and   an insulating material between the lower surface and the second substrate of the capacitor component, wherein the insulating material comprises a particle having a diameter equal to the first thickness minus the second thickness, plus or minus 20%.   
     
     
         2 . The device of  claim 1 , wherein the first substrate further has therein an electronic integrated circuit. 
     
     
         3 . The device of  claim 2 , wherein the electronic integrated circuit is a central processing unit (CPU). 
     
     
         4 . The device of  claim 1 , wherein the first substrate further has therein a photonic integrated circuit. 
     
     
         5 . The device of  claim 1 , wherein the insulating material is an epoxy resin. 
     
     
         6 . The device of  claim 1 , wherein the particle comprises aluminum oxide (Al 2 O 3 ). 
     
     
         7 . The device of  claim 1 , wherein the particle comprises an oxide. 
     
     
         8 . The device of  claim 1 , wherein the particle is thermally conductive. 
     
     
         9 . The device of  claim 1 , wherein the particle is thermally metallic. 
     
     
         10 . The device of  claim 1 , wherein the particle is thermally insulating. 
     
     
         11 . The device of  claim 1 , further comprising a mold compound sandwiched between the capacitor component and the first substrate. 
     
     
         12 . A multi-die assembly, comprising:
 a substrate package having an upper surface, a lower surface, and a first thickness;   an integrated circuit (IC) in the substrate package;   a capacitor component in the substrate package, the capacitor component exposed at the upper surface and comprising a trench that extends orthogonally downward in a second substrate therefrom, wherein the capacitor component has a second thickness that is less than the first thickness;   an insulating material between the lower surface and the second substrate of the capacitor component, wherein the insulating material comprises a particle having a diameter equal to the first thickness minus the second thickness, plus or minus 20%; and   a plurality of conductive contacts on the upper surface of the substrate package and attached to the IC and the capacitor component.   
     
     
         13 . The multi-die assembly of  claim 12 , further comprising a printed circuit board attached to the plurality of conductive contacts. 
     
     
         14 . The multi-die assembly of  claim 13 , further comprising an integrated circuit die attached to the printed circuit board. 
     
     
         15 . The multi-die assembly of  claim 14 , further comprising a memory device attached to the printed circuit board. 
     
     
         16 . The multi-die assembly of  claim 15 , further comprising a cooling component attached to the substrate package. 
     
     
         17 . A method, comprising:
 fabricating an integrated circuit on a silicon substrate;   identifying a capacitor component with a trench capacitor to integrate with the integrated circuit;   creating a cavity in the silicon substrate to accommodate the capacitor component;   determining a magnitude of a gap defined as a difference between a thickness of the silicon substrate and a thickness of the capacitor component; and   selecting an insulating material with a minimum bond line that matches the magnitude.   
     
     
         18 . The method of  claim 17 , further comprising:
 attaching a temporary carrier to a lower surface of the silicon substrate;   dispensing the insulating material in the cavity on the temporary carrier; and   placing the capacitor component on the insulating material in the cavity.   
     
     
         19 . The method of  claim 18 , wherein selecting the insulating material with the minimum bond line includes selecting a particle type that has a diameter equal to the magnitude, plus or minus 20%. 
     
     
         20 . The method of  claim 18  wherein selecting the insulating material with the minimum bond line includes selecting a particle type that is an oxide.