US2025201673A1PendingUtilityA1
Semiconductor device and method of manufacturing the same
Est. expiryDec 15, 2043(~17.4 yrs left)· nominal 20-yr term from priority
Inventors:Kazuki Matsumura
H10W 90/756H10W 90/736H10W 72/5525H10W 72/01571H10W 72/01561H10W 72/884H10W 72/525H10W 74/114H10W 70/429H10W 72/075H10W 99/00H10W 72/073H10W 72/50H10W 72/30H10W 70/481H10W 70/465H10W 70/417H10W 74/111H10W 20/40H10W 74/10H10W 72/071H10W 74/01H10W 70/24H01L 2924/13091H01L 2924/13055H01L 2224/73265H01L 2224/48245H01L 2224/45347H01L 2224/45147H01L 2224/4381H01L 2224/4351H01L 2224/32245H01L 24/73H01L 24/32H01L 24/48H01L 24/45H01L 24/43H01L 23/49555H01L 23/3121H01L 23/49513
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Claims
Abstract
A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wire electrically connected with the source electrode pad of the semiconductor chip; and a sealing body sealing the semiconductor chip and the wire. The wire and the source electrode pad are made of different types of metals to each other. A wire bonding layer made of sintered metal is interposed between the source electrode pad and the wire. The wire is electrically connected with the source electrode pad via the wire bonding layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising:
a die pad; a lead spaced apart from said die pad; a semiconductor chip mounted on said die pad via a die bonding material, said semiconductor chip including a first electrode pad; a wire electrically connected with each of said lead and said first electrode pad of said semiconductor chip; and a sealing body sealing said semiconductor chip, said die bonding material and said wire, wherein said first electrode pad and said wire are made of different types of metals to each other, wherein a wire bonding layer made of sintered metal is interposed between said first electrode pad and said wire, and wherein said wire is electrically connected with said first electrode pad via said wire bonding layer.
2 . The semiconductor device according to claim 1 ,
wherein said wire is made of copper, and wherein said first electrode pad is mainly made of aluminum.
3 . The semiconductor device according to claim 2 , wherein said wire bonding layer is made of sintered copper.
4 . The semiconductor device according to claim 3 ,
wherein a first metal film is interposed between said wire bonding layer and said first electrode pad, and wherein a metal film made of one of gold, silver, copper and nickel is formed at a portion, which is in contact with said wire bonding layer, of said first metal film.
5 . The semiconductor device according to claim 1 , wherein said die bonding material is made of sintered metal.
6 . The semiconductor device according to claim 5 ,
wherein said wire is made of copper, wherein said first electrode pad is mainly made of aluminum, and wherein each of said wire bonding layer and said die bonding material is made of sintered copper.
7 . The semiconductor device according to claim 5 ,
wherein said semiconductor chip has:
a first surface facing said die pad,
a second surface opposite said first surface, and
a second electrode pad formed on said second surface,
wherein a first metal film is interposed between said wire bonding layer and said first electrode pad, wherein a metal film made of one of gold, silver, copper and nickel is formed at a portion, which is in contact with said wire bonding layer, of said first metal film, and wherein a metal film made of one of gold, silver, copper and nickel is formed at a portion, which is in contact with said die bonding material, of said second electrode pad.
8 . The semiconductor device according to claim 5 , wherein a thickness of said wire bonding layer is larger than a thickness of said die bonding material.
9 . The semiconductor device according to claim 1 ,
wherein said semiconductor chip includes a power transistor made of one of power MOSFET and IGBT, and wherein said first electrode pad is electrically connected with a source of said power MOSFET or an emitter of said IGBT.
10 . A method of manufacturing a semiconductor device, comprising steps of:
(a) preparing a lead frame including a die pad; (b) applying a first paste material onto said die pad; (c) mounting a semiconductor chip on said first paste material, said semiconductor chip having a first electrode pad; (d) arranging a second paste material containing multiple metal particles on said first electrode pad of said semiconductor chip; (e) sintering said multiple metal particles contained in said second paste material by heating, thereby forming a wire bonding layer; and (f) bonding a wire to said wire bonding layer, said wire being made of metal which is a different type from said first electrode pad.
11 . The method according to claim 10 ,
wherein said first paste material is made of a material which is the same as a material of said second paste material, and wherein in said step of (e), by heating said first paste material, multiple metal particles contained in said first paste material are sintered, thereby forming a die bonding material fixing said semiconductor chip on said die pad.
12 . The method according to claim 11 ,
wherein each of said multiple metal particles is a copper particle, and wherein after said step of (e) and before said (f) step, said wire bonding layer is cleaned by using an acidic cleaning material.
13 . The method according to claim 10 , wherein in said step of (f), said wire and said wire bonding layer are bonded to each other under a condition that an ultrasonic wave and a load are applied to said wire.
14 . The method according to claim 10 ,
wherein said wire is made of copper, and wherein said first electrode pad is mainly made of aluminum.
15 . The method according to claim 13 , wherein each of said multiple metal particles is a copper.
16 . The method according to claim 10 , wherein the step of (e) is performed under one of a reduced pressure treatment atmosphere, an inert gas atmosphere, and a reducing atmosphere.Join the waitlist — get patent alerts
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