Selective deposition for mitigating corner loss in semiconductor fabrication
Abstract
Some aspects of the inventive concepts relate to methods for mitigating corner loss in semiconductor fabrication. The methods can include performing a first etching process to selectively expose corner portions of a first material layer within a multi-layered semiconductor structure by removing portions of a second material layer adjacent to the first material layer. The exposed corner portions can undergo a surface treatment comprising a pretreatment process to modify chemical or physical properties and functionalization with a surface-modifying agent to enable selective deposition. A protective material can be selectively deposited onto the corner portions of the first material layer. In some aspects, a second etching process can be performed to remove additional portions of the multi-layered structure, with the protective material mitigating etch-induced degradation or structural impacts on the corner portions, thereby enhancing precision and reliability in semiconductor device fabrication.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for mitigating corner loss in semiconductor fabrication, the method comprising:
performing a first timed etching process to selectively remove portions of a first material layer (SiO 2 ) of a substrate having a multi-layered semiconductor structure, wherein the first etching process exposes corner portions of a second material layer (SiN) adjacent to the first material layer; applying a surface treatment to the substrate, wherein the surface treatment inhibits deposition of a hardmask material on the first material layer and facilitates deposition of the hardmask material on the second material layer; depositing the hardmask material onto the corner portions of the second material layer, wherein deposition of the hardmask material is selective due to at least one of chemical selectivity, surface reactivity, or steric hindrance provided by the surface treatment; performing a second etching process to selectively remove additional portions of the substrate, wherein the hardmask material mitigates etch-induced degradation of the corner portions during the second etching process.
2 . The method of claim 1 , wherein the pretreatment process comprises a plasma process to remove native oxide layers from the corner portions of the first material layer, and wherein the surface-modifying agent comprises an aminosilane small molecule inhibitor.
3 . The method of claim 2 , wherein the aminosilane small molecule inhibitor comprises silane-based inhibitors, including dimethylamino-trimethylsilane (DMATMS), hexamethyldisilazane (HMDS), or tris(dimethylamino)silane (TDMAS).
4 . The method of claim 1 , wherein the first etching process employs a fluorinated etchant to selectively remove the portions of the second material layer.
5 . The method of claim 4 , wherein the fluorinated etchant comprises a CH x F y -type fluorinated etchant, wherein x and y are integers representing a number of hydrogen and fluorine atoms, respectively.
6 . The method of claim 1 , wherein depositing the hardmask material comprises utilizing a first precursor of titanium tetrachloride (TiCl 4 ) with ammonia (NH 3 ) or a second precursor of a mixture of nitrogen (N 2 ) and hydrogen (H 2 ), and water vapor (H 2 O).
7 . The method of claim 1 , wherein depositing the hardmask material comprises utilizing a precursor of tetrakis(dimethylamino)titanium (TDMAT) or bis(ethylmethylamino)titanium (BEMAT).
8 . The method of claim 1 , wherein the hardmask material comprises titanium oxynitride (TiON), titanium nitride (TiN), titanium dioxide (TiO 2 ), hafnium oxynitride (HfON), or hafnium dioxide (HfO 2 ).
9 . The method of claim 1 , wherein depositing the hardmask material comprises utilizing an atomic layer deposition (ALD) process, wherein the ALD process includes alternating exposures of titanium tetrachloride (TiCl 4 ) and water vapor (H 2 O) to form the hardmask material.
10 . The method of claim 1 , wherein the second etching process utilizes a chlorine-based etchant comprising chlorine (Cl 2 ), boron trichloride (BCl 3 ), or a mixture thereof, or a fluorine-based etchant comprising compounds with the formula C x H γ F z , including CF 4 or CHF 3 .
11 . The method of claim 1 , further comprising depositing a conductive material into regions exposed by the second etching process to form electrical interconnects, wherein the conductive material comprises tungsten, copper, cobalt, or alloys thereof.
12 . The method of claim 11 , further comprising removing the hardmask material prior to depositing the conductive material.
13 . The method of claim 1 , wherein the surface treatment comprises applying a small molecule inhibitor to selectively functionalize the first material layer, wherein the small molecule inhibitor inhibits deposition of the hardmask material on the first material layer and allows selective deposition onto the exposed corner portions of the second material layer after the first timed etching process has partially removed the first material layer to expose the second material layer.
14 . The method of claim 1 , wherein the second material layer comprises silicon nitride (SiN x ), amorphous silicon, doped polysilicon, silicon carbide (SiC), or silicon oxynitride (SiON).
15 . The method of claim 1 , wherein the surface treatment and hardmask material deposition are performed in a continuous processing chamber to limit reoxidation of the corner portions of the first material layer.
16 . The method of claim 1 , wherein the hardmask material enhances etch selectivity between the first material layer and the second material layer during the second etching process.
17 . The method of claim 1 , wherein the hardmask material is conformally deposited onto the corner portions of the first material layer, achieving a step coverage of at least 90%.
18 . A system for semiconductor fabrication, the system comprising:
a processing chamber configured to perform a first etching process to selectively remove portions of a first material layer of a substrate having a multi-layered semiconductor structure, wherein the first etching process exposes corner portions of a second material layer adjacent to the first material layer; a plasma treatment unit within the chamber, configured to pretreat the substrate with a surface treatment, wherein the surface treatment inhibits deposition of a hardmask material on the first material layer and facilitates deposition of the hardmask material on the second material layer; a deposition system configured to deposit the hardmask material onto the corner portions of the second material layer, wherein deposition of the hardmask material is selective due to at least one of chemical selectivity, surface reactivity, or steric hindrance provided by the surface treatment; and an etching module configured to perform a second etching process to selectively remove additional portions of the substrate, wherein the hardmask material mitigates etch-induced degradation of the corner portions during the second etching process.
19 . A semiconductor structure fabricated by a method comprising:
performing a first timed etching process to selectively remove portions of a first material layer of a substrate having a multi-layered semiconductor structure, wherein the first etching process exposes corner portions of a second material layer adjacent to the first material layer; applying a surface treatment to the substrate, wherein the surface treatment inhibits deposition of a hardmask material on the first material layer and facilitates deposition of the hardmask material on the second material layer; depositing the hardmask material onto the corner portions of the second material layer, wherein deposition of the hardmask material is selective due to at least one of chemical selectivity, surface reactivity, or steric hindrance provided by the surface treatment; performing a second etching process to selectively remove additional portions of the substrate, wherein the hardmask material mitigates etch-induced degradation of the corner portions during the second etching process.Join the waitlist — get patent alerts
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