Interconnect structures of semiconductor device and methods of forming the same

Abstract

A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

What is claimed is: 
     
         1 . An interconnect structure, comprising:
 an etching stop layer, a dielectric layer and an insert layer over a substrate;   a conductive line laterally surrounded by the etching stop layer, the dielectric layer, and the insert layer; and   a via below the conductive line,   wherein a material of the insert layer is different from the dielectric layer and the etching stop layer,   wherein a bottom surface of the insert layer is higher than a bottom surface of the conductive line.   
     
     
         2 . The interconnect structure of  claim 1 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the dielectric layer. 
     
     
         3 . The interconnect structure of  claim 1 , wherein the insert layer has a dielectric constant less than a dielectric constant of the etching stop layer. 
     
     
         4 . The interconnect structure of  claim 1 , wherein the insert layer and the dielectric layer contain a first atom and a second atom, and the etching stop layer is free of the first atom and the second atom. 
     
     
         5 . The interconnect structure of  claim 4 , wherein the etching stop layer contain a third atom, and the insert layer and the dielectric layer are free of the third atom. 
     
     
         6 . The interconnect structure of  claim 5 , wherein the first atom comprises silicon, the second atom comprises carbon, and the third atom comprises aluminum. 
     
     
         7 . The interconnect structure of  claim 1 , wherein the insert layer comprises silicon nitride, silicon oxynitride, silicon oxycarbide, or combinations thereof, and the etching stop layer comprises aluminum oxide. 
     
     
         8 . The interconnect structure of  claim 1 , further comprising:
 another conductive line laterally surrounded by the etching stop layer, the dielectric layer, and the insert layer; and   a stack laterally between the conductive line and the another conductive line, wherein the stack comprises a portion of the dielectric layer and a portion of the insert layer, and the stack has an aspect ratio greater than 2.   
     
     
         9 . The interconnect structure of  claim 1 , wherein the conductive line comprises a first conductive bulk layer and a first barrier layer around sidewalls and a bottom of the first conductive bulk layer, and sidewalls of the first barrier layer of the conductive line are in contact with the insert layer and the etching stop layer. 
     
     
         10 . The interconnect structure of  claim 9 , wherein the first barrier layer is sandwiched between the first conductive bulk layer and the via. 
     
     
         11 . The interconnect structure of  claim 10 , wherein the via comprises a second conductive bulk layer and a second barrier layer around sidewalls and a bottom of the second conductive bulk layer, the first barrier layer is sandwiched between the first conductive bulk layer and the second conductive bulk layer, and the second barrier layer is separated from the etching stop layer and the insert layer. 
     
     
         12 . An interconnect structure, comprising:
 an etching stop layer, a dielectric layer and an insert layer over a substrate;   a conductive line laterally surrounded by the dielectric layer, and the insert layer; and   a via below the conductive line and laterally surrounded by the etching stop layer,   wherein a material of the insert layer is different from the dielectric layer and the etching stop layer.   
     
     
         13 . The interconnect structure of  claim 12 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the dielectric layer. 
     
     
         14 . The interconnect structure of  claim 12 , wherein the insert layer has a dielectric constant less than a dielectric constant of the etching stop layer. 
     
     
         15 . The interconnect structure of  claim 12 , wherein the insert layer comprises silicon nitride, silicon oxynitride, silicon oxycarbide, or combinations thereof, and the etching stop layer comprises aluminum oxide. 
     
     
         16 . The interconnect structure of  claim 12 , wherein the conductive line is a part of a dual damascene, and the via is another part of the dual damascene. 
     
     
         17 . An interconnect structure, comprising:
 an etching stop layer, a dielectric layer and an insert layer over a substrate;   a plurality of conductive lines each embedded in the etching stop layer, the dielectric layer, and the insert layer; and   a stack laterally between the plurality of conductive lines and on the etching stop layer, wherein the stack has an aspect ratio greater than 2, and a material of the insert layer is different from the dielectric layer and the etching stop layer.   
     
     
         18 . The interconnect structure of  claim 17 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the dielectric layer, and equal to or less than a Young's modulus of the etching stop layer. 
     
     
         19 . The interconnect structure of  claim 17 , wherein the insert layer has a dielectric constant less than a dielectric constant of the etching stop layer, and greater than a dielectric constant of the dielectric layer. 
     
     
         20 . The interconnect structure of  claim 17 , wherein the insert layer comprises silicon nitride, silicon oxynitride, silicon oxycarbide, or combinations thereof, and the etching stop layer comprises aluminum oxide.