Push-pull mechanisms for handling dataflow between circuit blocks

Abstract

Push-pull mechanisms for handling dataflow between circuit blocks are disclosed. In certain embodiments, a network of dataflow gaskets includes a source gasket coupled to a first circuit block and a destination gasket coupled to a second circuit block. The source gasket and the destination gasket are connected by a push mechanism that uses write channels to write data from the source gasket to the destination gasket, and a pull mechanism that uses read channels to read data from the source gasket to the destination gasket. The source gasket and the destination gasket can switch between a push mode and a pull mode to ease traffic based on data available to transfer at the source gasket and/or a space available to receive data in the destination gasket. For example, a transfer size register can be used to set a threshold to aid between the mode transitions.

What is claimed is: 
     
         1 . An integrated circuit (IC) comprising:
 a plurality of circuit blocks including a first circuit block and a second circuit block; and   a plurality of dataflow gaskets electrically connected by a network of gasket interconnect, the plurality of dataflow gaskets comprising a source gasket comprising an output memory coupled to the first circuit block, and a destination gasket comprising an input memory coupled to the second circuit block,   wherein the source gasket is configured to communicate with the destination gasket over the network using a push mode and a pull mode,   wherein a transition from the pull mode to the push mode occurs in response to a data low trigger signal activated by the source gasket and a space high qualifier signal activated by the destination gasket, and   wherein a transition from the push mode to the pull mode occurs in response to a space low trigger signal activated by the destination gasket and a data high qualifier signal activated by the source gasket.   
     
     
         2 . The IC of  claim 1 , wherein the data low trigger signal is activated when available data in the output memory of the source gasket is less than a data low threshold. 
     
     
         3 . The IC of  claim 2 , wherein the space high qualifier signal is activated when available space in the input memory of the destination gasket is greater than a space high threshold. 
     
     
         4 . The IC of  claim 3 , wherein the space low trigger signal is activated when the available space in the input memory of the destination gasket is less than a space low threshold. 
     
     
         5 . The IC of  claim 4 , wherein the data high qualifier signal is activated when the available data in the output memory of the source gasket is greater than a data high threshold. 
     
     
         6 . The IC of  claim 3 , wherein the space high threshold is twice the data low threshold. 
     
     
         7 . The IC of  claim 1 , wherein the network connecting the source gasket to the destination gasket includes a read address channel and a read data channel, wherein the data low trigger signal is communicated over the read data channel and the space high qualifier signal is communicated over the read address channel. 
     
     
         8 . The IC of  claim 7 , wherein the network connecting the source gasket to the destination gasket further includes a write address channel, a write data channel, and a write response channel, wherein the space low trigger signal is communicated over the write response channel and the data high qualifier signal is communicated over the write data channel. 
     
     
         9 . The IC of  claim 1 , wherein in the push mode the source gasket serves as a master and the destination gasket serves as a slave, and in the pull mode the source gasket serves as the slave and the destination gasket serves as the master. 
     
     
         10 . The IC of  claim 1 , wherein in the push mode write data flows over a data write channel of the network from the output memory of the source gasket to the input memory of the destination gasket. 
     
     
         11 . The IC of  claim 1 , wherein in the pull mode read data flows through the network over a data read channel from the output memory of the source gasket to the input memory of the destination gasket. 
     
     
         12 . The IC of  claim 1 , wherein the output memory of the source gasket is a first circular buffer, and the input memory of the destination gasket is a second circular buffer. 
     
     
         13 . The IC of  claim 1 , wherein the first circuit block comprises a digital signal processor, a central processing unit, a neural processing unit, a reconfigurable compute unit, or an analog-to-digital converter (ADC). 
     
     
         14 . The IC of  claim 13 , wherein the second circuit block comprises a digital signal processor, a central processing unit, a neural processing unit, a reconfigurable compute unit, or a digital-to-analog converter (DAC). 
     
     
         15 . A method of handling dataflow between circuit blocks, the method comprising:
 communicating between a source gasket and a destination gasket over a network using a push mode and a pull mode, the source gasket comprising an output memory coupled to a first circuit block and the destination gasket comprising an input memory coupled to a second circuit block;   providing a transition from the pull mode to the push mode in response to a data low trigger signal activated by the source gasket and a space high qualifier signal activated by the destination gasket, and   providing a transition from the push mode to the pull mode in response to a space low trigger signal activated by the destination gasket and a data high qualifier signal activated by the source gasket.   
     
     
         16 . The method of  claim 15 , wherein the data low trigger signal is activated when available data in the output memory of the source gasket is less than a data low threshold. 
     
     
         17 . The method of  claim 16 , wherein the space high qualifier signal is activated when available space in the input memory of the destination gasket is greater than a space high threshold. 
     
     
         18 . The method of  claim 17 , wherein the space low trigger signal is activated when the available space in the input memory of the destination gasket is less than a space low threshold. 
     
     
         19 . The method of  claim 18 , wherein the data high qualifier signal is activated when the available data in the output memory of the source gasket is greater than a data high threshold. 
     
     
         20 . The method of  claim 15 , wherein the network connecting the source gasket to the destination gasket includes a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel, wherein the data low trigger signal is communicated over the read data channel and the space high qualifier signal is communicated over the read address channel, and the space low trigger signal is communicated over the write response channel and the data high qualifier signal is communicated over the write data channel.