Apparatus and method for controlling and debugging hardware lockstep mis-compares

Abstract

An apparatus and method for controlling and debugging hardware lockstep mis-compares. For example, one embodiment of a processor comprises: a plurality of processing elements operable in a redundancy mode, the plurality of processing elements to each execute a same plurality of instructions and produce a corresponding plurality of result signals; comparator circuitry to compare corresponding result signals of the plurality of result signals, the comparator circuitry to generate one or more failure indications when a first one or more result signals produced by a first processing element are different from a corresponding second one or more result signals produced by a second processing element; and masking circuitry to mask a first failure indication of the one or more failure indications when a corresponding mask bit of a mask matrix is set to a first value.

What is claimed is: 
     
         1 . A processor, comprising:
 a plurality of processing elements operable in a redundant processing mode, each processing element of the plurality of processing elements to execute an identical plurality of instructions and produce a corresponding plurality of result signals;   comparator circuitry to compare corresponding result signals of the corresponding plurality of result signals, the comparator circuitry to generate one or more failure indications when a first one or more result signals produced by a first processing element differ from a corresponding second one or more result signals produced by a second processing element; and   masking circuitry to mask a first failure indication of the one or more failure indications when a corresponding mask bit of a mask matrix is set to a first value.   
     
     
         2 . The processor of  claim 1  wherein the mask matrix is generated based on a combination of signal-level mask bits and group-level mask bits. 
     
     
         3 . The processor of  claim 2  wherein the comparator circuitry comprises a plurality of comparators, each comparator of the plurality of comparators configured to perform comparisons of a group of result signals of the corresponding plurality of result signals, each group of result signals associated with a group-level mask bit of a plurality of group-level mask bits. 
     
     
         4 . The processor of  claim 3  wherein each group of result signals includes result signals of a particular type. 
     
     
         5 . The processor of  claim 3  wherein each group of result signals includes result signals associated with a separate key characteristic indicator of the plurality of processing elements. 
     
     
         6 . The processor of  claim 3  wherein the corresponding mask bit of the mask matrix is set to the first value only when a corresponding signal level mask bit of a plurality of signal level mask bits and a corresponding group-level mask bit of the plurality of group-level mask bits are both set to the first value. 
     
     
         7 . The processor of  claim 6  wherein the first value comprises a binary value of 1. 
     
     
         8 . The processor of  claim 1  wherein the masking circuitry is to mask the first failure indication by changing the first failure indication to a pass indication. 
     
     
         9 . The processor of  claim 3  wherein the plurality of group-level mask bits and the signal-level mask bits are to be used to identify a source of the one or more failure indications. 
     
     
         10 . A method comprising:
 operating a plurality of processing elements in a redundant processing mode, each processing element of the plurality of processing elements to execute an identical plurality of instructions and produce a corresponding plurality of result signals;   comparing corresponding result signals of the corresponding plurality of result signals;   generating one or more failure indications when a first one or more result signals produced by a first processing element differ from a corresponding second one or more result signals produced by a second processing element; and   masking a first failure indication of the one or more failure indications when a corresponding mask bit of a mask matrix is set to a first value.   
     
     
         11 . The method of  claim 10  further comprising:
 generating the mask matrix based on a combination of signal-level mask bits and group-level mask bits. 
 
     
     
         12 . The method of  claim 11  wherein comparing is performed with a plurality of comparators, each comparator of the plurality of comparators configured to perform comparisons of a group of result signals of the corresponding plurality of result signals, each group of result signals associated with a group-level mask bit of a plurality of group-level mask bits. 
     
     
         13 . The method of  claim 12  wherein each group of result signals includes result signals of a particular type. 
     
     
         14 . The method of  claim 12  wherein each group of result signals includes result signals associated with a separate key characteristic indicator of the plurality of processing elements. 
     
     
         15 . The method of  claim 12  wherein the corresponding mask bit of the mask matrix is set to the first value only when a corresponding signal level mask bit of a plurality of signal-level mask bits and a corresponding group-level mask bit of the plurality of group-level mask bits are both set to the first value. 
     
     
         16 . The method of  claim 15  wherein the first value comprises a binary value of 1. 
     
     
         17 . The method of  claim 10  wherein masking the first failure indication includes changing the first failure indication to a pass indication. 
     
     
         18 . The method of  claim 12  further comprising:
 identifying a source of the one or more failure indications based on the plurality of group-level mask bits and the signal-level mask bits. 
 
     
     
         19 . A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations, comprising:
 operating a plurality of processing elements in a redundant processing mode, each processing element of the plurality of processing elements to execute an identical plurality of instructions and produce a corresponding plurality of result signals;   comparing corresponding result signals of the corresponding plurality of result signals;   generating one or more failure indications when a first one or more result signals produced by a first processing element differ from a corresponding second one or more result signals produced by a second processing element; and   masking a first failure indication of the one or more failure indications when a corresponding mask bit of a mask matrix is set to a first value.   
     
     
         20 . The machine-readable medium of  claim 19  further comprising program code to cause the machine to perform the operation of:
 generating the mask matrix based on a combination of signal-level mask bits and group-level mask bits.