Digital-to-analog converter

Abstract

The present disclosure relates to a method of controlling a digital-to-analog converter, DAC, system. The DAC system includes a plurality of DAC cores connected in parallel with the outputs of the DAC cores coupled so as to provide a combined analog output. Each DAC core receives a digital signal which is a modified version of a digital input provided to the DAC system. By providing modified digital signals to the DAC cores and using a plurality of DAC cores, the monotonicity of the DAC system may be improved.

What is claimed is: 
     
         1 . A method of digital-to-analog conversion, the method comprising:
 receiving a digital input at an input of a digital-to-analog converter, DAC, system, the DAC system configured to provide P bits of monotonicity; and   converting the digital input to an analog output, wherein converting the digital input to the analog output comprises:
 providing to each respective DAC core of a plurality of DAC cores a respective digital signal based on the digital input, wherein each DAC core of the plurality of DAC cores is an N bit DAC core and has M bits of monotonicity, wherein the plurality of DAC cores comprises 2 P-M  DAC cores, and wherein when the respective digital signal has more than N bits, configuring a respective DAC core to receive an input with more than N bits; 
 converting, using each of the plurality of DAC cores, the respective digital signal to a respective analog signal; and 
 combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output. 
   
     
     
         2 . The method of  claim 1 , wherein each DAC core of the plurality of DAC cores is configured to receive an input with more bits than the DAC core is programmed to accept. 
     
     
         3 . The method of  claim 1 , wherein the respective digital signal provided to each respective DAC core of the plurality of DAC cores is formed by adding a first binary signal based on the digital input and an adjustment value. 
     
     
         4 . The method of  claim 3 , wherein the adjustment values for the DAC cores have an average value equal to the [(N−1-M):(N−P)] bits of the digital input. 
     
     
         5 . The method of  claim 3 , wherein the first binary signal comprises the M most significant bits of the digital input. 
     
     
         6 . The method of  claim 5 , wherein the first binary signal comprises the M most significant bits of the digital input, with the remaining bits of the digital input set to zero. 
     
     
         7 . The method of  claim 3 , wherein the system adds P-M bits of monotonicity. 
     
     
         8 . The method of  claim 7 , wherein an average of the respective adjustment values of the respective digital signals is the same as the value of the P-M bits for which monotonicity is added. 
     
     
         9 . The method of  claim 3 , wherein the bits of the digital input are numbered bits [N−1:0], and wherein the first binary signal is obtained by concatenating:
 bits [N−1:N-M] of the digital input; and 
 P-M bits, wherein the bits are set as zero. 
 
     
     
         10 . The method of  claim 9 , wherein, if N−1-P≥0, the first binary signal further comprises the concatenation of bits [N−1-P:0] of the digital input. 
     
     
         11 . The method of  claim 3 , wherein the method further comprises obtaining the adjustment value, wherein the adjustment value is either 0 or 2 N-M . 
     
     
         12 . The method of to  claim 3 , wherein the plurality of DAC cores are numbered i=[2 P-M -1:0], and wherein if the value of the [(N−1-M):(N−P)] bits of the digital input are greater than i, the adjustment value for the i th  DAC core is 2 N-M . 
     
     
         13 . The method of  claim 12 , wherein if the value of the [(N−1-M):(N−P)] bits of the digital input are less than or equal to i, the adjustment value for the i th  DAC core is 0. 
     
     
         14 . The method of  claim 1 , further comprising configuring each respective DAC core such that it is capable of receiving 2 N +1 input codes. 
     
     
         15 . The method of  claim 14 , wherein the method further comprises connecting a termination leg of a respective DAC core to a reference voltage when the DAC overflows. 
     
     
         16 . The method of  claim 14 , wherein, if the respective DAC core would overflow when supplied with the respective digital signal, the method further comprises changing a connection of a termination leg of the respective DAC core from a first reference voltage to a second reference voltage. 
     
     
         17 . The method of  claim 3 , wherein if addition of the first binary signal and the adjustment value would result in respective digital signal with a value greater than 2 N −1, the method further comprises:
 modifying the first binary signal to be a concatenation of the M most significant bits of the digital input and N-M bits set to zero; 
 modifying the adjustment value to be 2 N-M −1, and 
 changing a connection of a termination leg of the respective DAC core from a first reference voltage to a second reference voltage. 
 
     
     
         18 . A digital-to-analog converter, DAC, system configured to implement the method of  claim 1 , receiving a digital input and outputting an analog output, the DAC system configured to provide P bits of monotonicity, the DAC system comprising:
 a plurality of DAC cores.   
     
     
         19 . A method of digital-to-analog conversion, the method comprising:
 receiving a digital input at an input of a digital-to-analog converter, DAC, system, the DAC system configured to provide P bits of monotonicity; and   converting the digital input to an analog output, wherein converting the digital input to the analog output comprises:
 providing to each respective DAC core of a plurality of DAC cores a respective digital signal based on the digital input, wherein each DAC core of the plurality of DAC cores is an N bit DAC core and has M bits of monotonicity, wherein the plurality of DAC cores comprises 2 P-M  DAC cores, and wherein all the DAC cores of the plurality of DAC cores is configured to support an overrange, wherein supporting an overrange comprises receiving an input with more bits than the DAC core is configured to accept; 
 converting, using each of the plurality of DAC cores, the respective digital signal to a respective analog signal; and 
 combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output. 
   
     
     
         20 . A method of digital-to-analog conversion, the method comprising:
 receiving a digital input at an input of a digital-to-analog converter, DAC, system, the DAC system configured to provide P bits of monotonicity; and   converting the digital input to an analog output, wherein converting the digital input to the analog output comprises:
 providing to each respective DAC core of a plurality of DAC cores a respective digital signal based on the digital input, wherein each DAC core of the plurality of DAC cores is an N bit DAC core and has M bits of monotonicity, wherein the plurality of DAC cores comprises 2 P-M  DAC cores; 
 converting, using each of the plurality of DAC cores, the respective digital signal to a respective analog signal; 
 combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output; and 
 if the respective DAC core would overflow when supplied with the respective digital signal, changing a connection of a termination leg of the respective DAC core from a first reference voltage to a second reference voltage.