Data processing method and apparatus

Abstract

A data processing method and apparatus are provided. The method includes obtaining, by a processor, a first request associated with a first input/output (I/O) task, determining, based on a first correspondence, a first processor core that is of the processor and that corresponds to the first request, where the first correspondence is a correspondence between an I/O task and a processor core, and determining, from a memory set corresponding to the first processor core, a target memory corresponding to the first request.

What is claimed is: 
     
         1 . A data processing method, comprising:
 obtaining, by a processor, a first request, wherein the first request is associated with a first input/output (I/O) task;   determining, based on a first correspondence, a first processor core that is of the processor and that corresponds to the first request, wherein the first correspondence is a correspondence between an I/O task and a processor core; and   determining, from a memory set corresponding to the first processor core, a target memory corresponding to the first request.   
     
     
         2 . The method according to  claim 1 , wherein the memory set corresponding to the first processor core is in a memory set of a first memory node, wherein the first memory node corresponds to at least one processor core, and wherein the at least one processor core comprises the first processor core. 
     
     
         3 . The method according to  claim 2 , wherein the determining the memory corresponding to the first request comprises:
 sending a second request to the first memory node, wherein the second request is associated with requesting to allocate the memory corresponding to the first request; and   receiving indication information of the target memory.   
     
     
         4 . The method according to  claim 2 , further comprising:
 determining, based on a second correspondence, the first memory node corresponding to the first processor core, wherein the second correspondence is a correspondence between a plurality of processor cores in the processor and a plurality of memory nodes, wherein the plurality of memory nodes comprise the first memory node, and wherein the plurality of processor cores comprise the first processor core.   
     
     
         5 . The method according to  claim 1 , wherein the determining the first processor core corresponding to the first request comprises:
 determining, based on the first correspondence, the first processor core corresponding to the first request in a first scheduling period, wherein the first correspondence is a scheduling result of an I/O task in a second scheduling period, and wherein the second scheduling period is a scheduling period before the first scheduling period.   
     
     
         6 . The method according to  claim 1 , further comprising:
 executing the first I/O task in the target memory.   
     
     
         7 . A data processing apparatus, comprising:
 a processor; and   a non-transitory storage connected to the processor and including program instructions, wherein the non-transitory storage and the program instructions are configured, with the processor, to cause the apparatus to at least,   obtain a first request, wherein the first request is associated with a first input/output I/O task;   determine, based on a first correspondence, a first processor core corresponding to the first request, wherein the first correspondence is a correspondence between an I/O task and a processor core; and   determine, from a memory set corresponding to the first processor core, a target memory corresponding to the first request.   
     
     
         8 . The apparatus according to  claim 7 , wherein the memory set corresponding to the first processor core is in a memory set of a first memory node, wherein the first memory node corresponds to at least one processor core, and wherein the at least one processor core comprises the first processor core. 
     
     
         9 . The apparatus according to  claim 8 , wherein causing the apparatus to determine the target memory corresponding to the first request comprises causing the apparatus to:
 send a second request to the first memory node, wherein the second request is associated with requesting to allocate the memory corresponding to the first request; and   receive indication information of the target memory corresponding to the first request.   
     
     
         10 . The apparatus according to  claim 8 , wherein the non-transitory storage and the program instructions are configured, with the processor, to further cause the apparatus to at least:
 determine, based on a second correspondence, the first memory node corresponding to the first processor core, wherein the second correspondence is a correspondence between a plurality of processor cores in the processor and a plurality of memory nodes, wherein the plurality of memory nodes comprise the first memory node, and wherein the plurality of processor cores comprise the first processor core.   
     
     
         11 . The apparatus according to  claim 7 , wherein causing the apparatus to determining the first processor core corresponding to the first request comprises causing the apparatus to:
 determine, based on the first correspondence, the first processor core corresponding to the first request in a first scheduling period, wherein the first correspondence is a scheduling result of an I/O task in a second scheduling period, and wherein the second scheduling period is a scheduling period before the first scheduling period.   
     
     
         12 . The apparatus according to  claim 7 , wherein non-transitory storage and the program instructions are configured, with the processor, to further cause the apparatus to at least:
 execute the first I/O task in the target memory.   
     
     
         13 . A chip, wherein the chip is coupled to a non-transitory storage, and is configured to read and execute program instructions stored in the storage to:
 obtain a first request, wherein the first request is associated with a first input/output I/O task; and   determine, based on a first correspondence, a first processor core corresponding to the first request, wherein the first correspondence is a correspondence between an I/O task and a processor core, wherein   determine, from a memory set corresponding to the first processor core, a target memory corresponding to the first request.   
     
     
         14 . The chip according to  claim 13 , wherein the memory set corresponding to the first processor core is in a memory set of a first memory node, wherein the first memory node corresponds to at least one processor core, and wherein the at least one processor core comprises the first processor core. 
     
     
         15 . The chip according to  claim 14 , wherein determining the target memory corresponding to the first request comprises:
 sending a second request to the first memory node, wherein the second request is associated with requesting to allocate the memory corresponding to the first request; and   receiving indication information of the target memory corresponding to the first request.   
     
     
         16 . The chip according to  claim 14 , wherein the chip is further configured to read and execute program instructions stored in the storage to:
 determine, based on a second correspondence, the first memory node corresponding to the first processor core, wherein the second correspondence is a correspondence between a plurality of processor cores in a processor and a plurality of memory nodes, wherein the plurality of memory nodes comprise the first memory node, and wherein the plurality of processor cores comprise the first processor core.   
     
     
         17 . The chip according to  claim 13 , wherein determining the first processor core corresponding to the first request comprises:
 determining, based on the first correspondence, the first processor core corresponding to the first request in a first scheduling period, wherein the first correspondence is a scheduling result of an I/O task in a second scheduling period, and wherein the second scheduling period is a scheduling period before the first scheduling period.   
     
     
         18 . The chip according to  claim 13 , wherein the chip is further configured to read and execute program instructions stored in the storage to:
 execute the first I/O task in the target memory.