Low latency automatic cross talk cancellation for led-based sensors

Abstract

Aspects of the present disclosure provide methods and apparatuses for operating an analog-to-digital converter. A method in accordance with an aspect of the present disclosure may comprise initializing a digital-to-analog converter (DAC) value of a DAC, determining whether an analog-to-digital converter (ADC) operates within a predetermined range based on an input to the DAC, initiating a conversion at a first ADC resolution when the ADC is operating within the predetermined range, and incrementally changing the DAC value when the ADC is not operating within the predetermined range.

What is claimed is: 
     
         1 . A method comprising:
 initializing a digital-to-analog converter (DAC) value of a DAC;   determining whether an analog-to-digital converter (ADC) operates within a predetermined range based on an input to the DAC;   initiating a conversion at a first ADC resolution when the ADC is operating within the predetermined range; and   incrementally changing the DAC value when the ADC is not operating within the predetermined range.   
     
     
         2 . The method of  claim 1 , wherein changing the DAC value changes a DAC current. 
     
     
         3 . The method of  claim 2 , wherein incrementally changing the DAC value comprises increasing the DAC value. 
     
     
         4 . The method of  claim 2 , wherein the input to the DAC is a photodiode current. 
     
     
         5 . The method of  claim 4 , wherein the ADC is a successive approximation register (SAR) based ADC. 
     
     
         6 . The method of  claim 5 , wherein the DAC value is based on a number of bits of the SAR based ADC. 
     
     
         7 . The method of  claim 6 , wherein the DAC value includes a settling time of a light-emitting diode. 
     
     
         8 . The method of  claim 7 , wherein the DAC value includes a conversion time of the ADC. 
     
     
         9 . An apparatus comprising:
 a digital-to-analog converter (DAC) having a DAC value;   a logic circuit coupled to the DAC;   an analog-to-digital converter (ADC) coupled to the DAC and the logic circuit, the ADC operating in a predetermined range based on an input to the DAC; and   a comparator circuit coupled to the logic circuit, the ADC, and the DAC, wherein the logic circuit and the comparator circuit initiate a conversion at a first ADC resolution when the ADC is operating within the predetermined range and incrementally change the DAC value when the ADC is not operating within the predetermined range.   
     
     
         10 . The apparatus of  claim 9 , wherein changing the DAC value changes a DAC current. 
     
     
         11 . The apparatus of  claim 10 , wherein incrementally changing the DAC value comprises increasing the DAC value. 
     
     
         12 . The apparatus of  claim 10 , wherein the input to the DAC is a photodiode current. 
     
     
         13 . The apparatus of  claim 12 , wherein the ADC is a successive approximation register (SAR) based ADC. 
     
     
         14 . The apparatus of  claim 13 , wherein the DAC value is based on a number of bits of the SAR based ADC. 
     
     
         15 . The apparatus of  claim 14 , wherein the DAC value includes a settling time of a light-emitting diode. 
     
     
         16 . The apparatus of  claim 15 , wherein the DAC value includes a conversion time of the ADC.