Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode facing the first semiconductor layer; a second gate electrode facing the first semiconductor layer and supplied with the same voltage as the first gate electrode; a first gate insulating layer between the first semiconductor layer and the first gate electrode, and between the first semiconductor layer and the second gate electrode; a second semiconductor layer sandwiching the first gate electrode with the first semiconductor layer; a third gate electrode facing the second semiconductor layer on an opposite side to the first gate electrode with respect to the second semiconductor layer, and overlapping the first gate electrode in a plan view; and a second gate insulating layer between the second semiconductor layer and the third gate electrode.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first semiconductor layer;   a first gate electrode facing the first semiconductor layer;   a second gate electrode facing the first semiconductor layer and supplied with a same voltage as the first gate electrode;   a first gate insulating layer between the first semiconductor layer and the first gate electrode, and between the first semiconductor layer and the second gate electrode;   a second semiconductor layer sandwiching the first gate electrode with the first semiconductor layer;   a third gate electrode facing the second semiconductor layer on an opposite side to the first gate electrode with respect to the second semiconductor layer, and overlapping the first gate electrode in a plan view; and   a second gate insulating layer between the second semiconductor layer and the third gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the second semiconductor layer includes an oxide semiconductor. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the second gate electrode does not overlap the third gate electrode in a plan view. 
     
     
         4 . The semiconductor device according to  claim 3 , further comprising:
 a first electrode connected to the first semiconductor layer in a first region; and   a second electrode connected to the first semiconductor layer in a second region on an opposite side to the first electrode with respect to the first gate electrode and the second gate electrode,   wherein the first gate electrode and the second gate electrode are separated in a cross-sectional view along a line connecting the first region and the second region.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein the first gate electrode is connected to the second gate electrode in a region not overlapping the first semiconductor layer in a plan view. 
     
     
         6 . The semiconductor device according to  claim 5 , further comprising:
 a first electrode connected to the first semiconductor layer in a first region; and   a second electrode connected to the first semiconductor layer in a second region on the opposite side to the first electrode with respect to the first gate electrode and the second gate electrode,   wherein a length of the second gate electrode is smaller than a length of the first gate electrode in a first direction connecting the first region and the second region.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein the first gate electrode and the second gate electrode are arranged in a same layer. 
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 a first electrode connected to the first semiconductor layer in a first region; and   a second electrode connected to the first semiconductor layer in a second region on an opposite side to the first electrode with respect to the first gate electrode and the second gate electrode,   wherein a length of the first gate electrode is larger than a length of the third gate electrode in a first direction connecting the first region and the second direction in a cross-sectional view along a line connecting the first region and the second region.   
     
     
         9 . The semiconductor device according to  claim 8 , further comprising:
 a third electrode connected to the second semiconductor layer in a third region; and   a fourth electrode connected to the second semiconductor layer in a fourth region on an opposite side to the third electrode with respect to the third gate electrode,   wherein   different voltages are supplied to the second electrode and the fourth electrode, and   the first electrode and the third electrode are electrically connected.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein the first electrode and the third gate electrode are arranged in the same layer.