US2025151207A1PendingUtilityA1
Wiring substrate and its manufacturing method
Assignee: SHANGHAI AVIC OPTOELECTONICS CO LTDPriority: Nov 8, 2023Filed: Nov 1, 2024Published: May 8, 2025
Est. expiryNov 8, 2043(~17.3 yrs left)· nominal 20-yr term from priority
Inventors:Akira Fujita
H10W 70/65H10W 20/40H10W 70/69H10W 90/701H05K 3/388H05K 1/111H05K 1/181H05K 2201/09472H05K 1/0271H01L 23/49838H01L 23/485
64
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A wiring substrate having, on a surface, a mounting pad for mounting a semiconductor device comprises a metal pad, an insulating layer, and a metal layer. A pad area of the mounting pad is defined by an opening section formed in the insulating layer. The wiring substrate further comprises an etching barrier layer provided between an upper surface of the metal pad and the insulating layer. The etching barrier layer is provided to surround a lower end of the opening section and extends outward from the lower end of the opening section to the outer periphery.
Claims
exact text as granted — not AI-modified1 . A wiring substrate having, on a surface, a mounting pad for mounting a semiconductor device, the wiring substrate comprising:
a metal pad provided on one of main surfaces of a base material; an insulating layer being provided to cover a side surface of the metal pad and at least part of an upper surface of the metal pad, and being provided with an opening section that exposes a part of the upper surface of the metal pad; and a metal layer provided on the metal pad exposed through the opening section, wherein a pad area of the mounting pad is defined by the opening section formed in the insulating layer, and the wiring substrate further comprises an etching barrier layer provided between the upper surface of the metal pad and the insulating layer, the etching barrier layer being provided to surround a lower end of the opening section and extending outward from the lower end of the opening section toward an outer periphery.
2 . The wiring substrate according to claim 1 , wherein at least an end of the etching barrier layer on the opening section side is in contact with the metal layer.
3 . The wiring substrate according to claim 1 , wherein the etching barrier layer is made of a metal different from a metal of which the metal pad is made.
4 . The wiring substrate according to claim 1 , wherein the etching barrier layer is made of an inorganic material.
5 . The wiring substrate according to claim 1 , wherein an end of the etching barrier layer on the opening section side protrudes toward a center of the opening section, relative to an inner peripheral surface of the opening section.
6 . The wiring substrate according to claim 1 , wherein the etching barrier layer extends to an outer peripheral side edge of the metal pad and covers the side surface of the metal pad.
7 . The wiring substrate according to claim 1 , wherein an end of the etching barrier layer on the opening section side is located at the lower end of the opening section.
8 . A manufacturing method of a wiring substrate having, on a surface, a mounting pad for mounting a semiconductor device, the manufacturing method includes steps of:
forming an etching barrier layer on a metal pad provided on one of main surfaces of a base material; forming an insulating layer covering a side surface of the metal pad and at least part of an upper surface of the metal pad, and being provided with an opening section that exposes a part of the upper surface of the metal pad; and forming a metal layer on the metal pad exposed through the opening section, wherein a pad area of the mounting pad is defined by the opening section formed in the insulating layer, and the etching barrier layer is formed to surround a lower end of the opening section and extend outward from the lower end of the opening section toward an outer periphery.
9 . The manufacturing method of the wiring substrate according to claim 8 , wherein the metal layer is formed to be in contact with at least an end of the etching barrier layer on the opening section side.
10 . The manufacturing method of the wiring substrate according to claim 8 , wherein the etching barrier layer is made of a metal different from a metal of which the metal pad is made.
11 . The manufacturing method of the wiring substrate according to claim 8 , wherein the etching barrier layer is made of an inorganic material.
12 . The manufacturing method of the wiring substrate according to claim 8 , wherein an end of the etching barrier layer on the opening section side is formed to protrude toward a center of the opening section, relative to an inner peripheral surface of the opening section.
13 . The manufacturing method of the wiring substrate according to claim 8 , wherein the etching barrier layer is formed to extend to an outer peripheral side edge of the metal pad and cover the side surface of the metal pad.
14 . The manufacturing method of the wiring substrate according to claim 8 , wherein an end of the etching barrier layer on the opening section side is formed to locate at the lower end of the opening section.Join the waitlist — get patent alerts
Track US2025151207A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.