Method for dicing a semiconductor wafer structure

Abstract

The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

What is claimed is: 
     
         1 . An integrated chip comprising:
 a semiconductor substrate;   a plurality of semiconductor devices disposed along the semiconductor substrate;   a first dielectric structure under the semiconductor substrate; and   a second dielectric structure over the semiconductor substrate,   wherein the semiconductor substrate has a first sidewall, a second sidewall over the first sidewall, a third sidewall between the first sidewall and the second sidewall, a first lower surface extending from a top of the first sidewall to a bottom of the third sidewall, and a first upper surface extending from a bottom of the second sidewall to a top of the third sidewall.   
     
     
         2 . The integrated chip of  claim 1 , wherein the first sidewall extends from the first lower surface to a bottom surface of the semiconductor substrate, and wherein the second sidewall extends from the first upper surface to a top surface of the semiconductor substrate. 
     
     
         3 . The integrated chip of  claim 1 , wherein the first dielectric structure has a first sidewall directly under the first sidewall of the semiconductor substrate, and wherein the second dielectric structure has a first sidewall directly over the second sidewall of the semiconductor substrate. 
     
     
         4 . The integrated chip of  claim 1 , wherein the first sidewall, the second sidewall, and a third sidewall of the semiconductor substrate extend along a first direction, and wherein the semiconductor substrate has a fourth sidewall extending along a second direction, different than the first direction, and extending from the first upper surface to the first lower surface of the semiconductor substrate. 
     
     
         5 . The integrated chip of  claim 1 , wherein a vertical distance from the top of the first sidewall to a bottom of the first sidewall is less than a vertical distance from the bottom of the second sidewall to a top of the second sidewall. 
     
     
         6 . The integrated chip of  claim 5 , wherein a vertical distance from the bottom of the third sidewall to the top of the third sidewall is different than the vertical distance from the top of the first sidewall to a bottom of the first sidewall and different than the vertical distance from the bottom of the second sidewall to a top of the second sidewall. 
     
     
         7 . The integrated chip of  claim 1 , wherein a lateral distance from the top of the third sidewall to the bottom of the second sidewall is different than a lateral distance from a bottom of the third sidewall to the top of the first sidewall. 
     
     
         8 . The integrated chip of  claim 1 , wherein the semiconductor substrate has a fourth sidewall facing away from the first sidewall, a fifth sidewall over the fourth sidewall and facing away from the second sidewall, and a sixth sidewall between the fourth sidewall and the fifth sidewall and facing away from the third sidewall. 
     
     
         9 . The integrated chip of  claim 8 , wherein the semiconductor substrate has a seventh sidewall extending from the first sidewall to the fourth sidewall, an eighth sidewall extending from the second sidewall to the fifth sidewall, and a ninth sidewall extending from the third sidewall to the sixth sidewall. 
     
     
         10 . An integrated chip comprising:
 a semiconductor substrate;   a plurality of semiconductor devices along the semiconductor substrate;   a first dielectric structure along a first side of the semiconductor substrate; and   a second dielectric structure along a second side of the semiconductor substrate, opposite the first side,   wherein a first pair of opposing sidewalls of the semiconductor substrate are separated by a first distance, wherein a second pair of opposing sidewalls of the semiconductor substrate are separated by a second distance, wherein a third pair of opposing sidewalls of the semiconductor substrate are separated by a third distance, wherein the third distance is greater than the second distance, wherein the third pair of opposing sidewalls are over the first pair of opposing sidewalls, and wherein the second pair of opposing sidewalls are over the third pair of opposing sidewalls.   
     
     
         11 . The integrated chip of  claim 10 , wherein the semiconductor substrate has a pair of upper cut surfaces that extend between bottoms of the second pair of opposing sidewalls and tops of the third pair of opposing sidewalls, wherein the semiconductor substrate has a pair of lower cut surfaces that extend between bottoms of the third pair of opposing sidewalls and tops of the first pair of opposing sidewalls, wherein the third pair of opposing sidewalls extend between the pair of upper cut surfaces and the pair of lower cut surfaces, respectively. 
     
     
         12 . The integrated chip of  claim 10 , wherein a pair of opposing sidewalls of the first dielectric structure are aligned with the first pair of opposing sidewalls of the semiconductor substrate, and wherein a pair of opposing sidewalls of the second dielectric structure are aligned with the second pair of opposing sidewalls of the semiconductor substrate. 
     
     
         13 . The integrated chip of  claim 10 , wherein the first pair of opposing sidewalls, the second pair of opposing sidewalls, and the third pair of opposing sidewalls are outermost sidewalls that delimit a boundary of the semiconductor substrate. 
     
     
         14 . The integrated chip of  claim 10 , wherein the third distance is different than the first distance. 
     
     
         15 . The integrated chip of  claim 10 , wherein the second distance is different than the first distance. 
     
     
         16 . The integrated chip of  claim 10 , wherein heights of the first pair of opposing sidewalls are less than heights of the second pair of opposing sidewalls. 
     
     
         17 . An apparatus comprising:
 a first semiconductor die having a first sidewall, a third sidewall over the first sidewall, and a second sidewall over the third sidewall; and   a second semiconductor die having a fourth sidewall facing the first sidewall and laterally spaced from the first sidewall by a first distance, a fifth sidewall facing the second sidewall and laterally spaced from the second sidewall by a second distance, and a sixth sidewall facing the third sidewall and laterally spaced from the third sidewall by a third distance, wherein the third distance is different than the first distance and the second distance.   
     
     
         18 . The apparatus of  claim 17 , wherein the first semiconductor die has a first upper surface extending from a bottom of the second sidewall to a top of the third sidewall, and wherein the second semiconductor die has a second upper surface extending from a bottom of the fifth sidewall to a top of the sixth sidewall. 
     
     
         19 . The apparatus of  claim 18 , wherein the first semiconductor die has a first lower surface extending from a top of the first sidewall to a bottom of the third sidewall, and wherein the second semiconductor die has a second lower surface extending from a top of the fourth sidewall to a bottom of the sixth sidewall. 
     
     
         20 . The apparatus of  claim 17 , wherein a vertical distance from a top of the first sidewall to a bottom of the first sidewall is less than a vertical distance between a top of the second sidewall and a bottom of the third sidewall.