Chip package unit and chip packaging method

Abstract

A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

1 - 9 . (canceled) 
     
     
         10 . A chip packaging method, including:
 providing a module including a plurality of chips, wherein the module includes a wafer, a substrate strip, a lead frame or a package material structure;   placing a stencil having hollow grooves on the module;   stacking a heat dissipation paste on the stencil, and scraping a portion of the stacked heat dissipation paste into the hollow grooves of the stencil, to dispose the portion of the heat dissipation paste on the module;   removing the stencil on the module, to leave the portion of the heat dissipation paste corresponding to the hollow grooves on the module;   curing the portion of the heat dissipation paste to form at least one heat dissipation paste curing layer corresponding to the hollow grooves; and   cutting the module into multiple chip units.   
     
     
         11 . The chip packaging method according to  claim 10 , further including: pressing and flattening the heat dissipation paste on the module. 
     
     
         12 . The chip packaging method according to  claim 10 , wherein the plurality of chips are provided on a base material, and after cutting the module into multiple chip units, each of the chip units and a corresponding portion of the base material are packaged by a package material. 
     
     
         13 . The chip packaging method according to  claim 12 , wherein the corresponding portion of base material includes the lead frame, the substrate strip, the package material structure, or a portion of the wafer. 
     
     
         14 . The chip packaging method according to  claim 10 , wherein a thermal conductivity of the at least one heat dissipation paste curing layer is higher than a thermal conductivity of the package material. 
     
     
         15 . The chip packaging method according to  claim 10 , wherein the at least one heat dissipation paste curing layer includes a plurality of heat dissipation paste curing layers. 
     
     
         16 . The chip packaging method according to  claim 15 , wherein the plurality of heat dissipation paste curing layers have different printed patterns. 
     
     
         17 . The chip packaging method according to  claim 16 , wherein each heat dissipation paste curing layer has a printed pattern, and the printed pattern includes at least one of the following patterns: a closed and fully-filled pattern, a dot matrix pattern, a strip matrix pattern, or a combination of two or more of the above patterns, or the plurality of heat dissipation paste curing layers form a stack of two or more of the above patterns. 
     
     
         18 . The chip packaging method according to  claim 10 , further comprising: disposing a graphene coating layer on the at least one heat dissipation paste curing layer.