Nonvolatile memory with isolation structure and method of forming the same

Abstract

A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.

1 . A non-volatile memory (NVM) structure, comprising:
 a semiconductor substrate;   first and second memory devices on the semiconductor substrate, each of the first and second memory devices including:
 a floating gate, 
 a tunnelling insulator under the floating gate, 
 an isolation layer over the floating gate, and 
 at least one of a select gate and a control gate over the isolation layer, 
   an erase gate shared by the first and second memory devices;   a source region under the erase gate; and   a shallow trench isolation structure between the erase gate and the source region.   
     
     
         2 . The NVM structure of  claim 1 , wherein the isolation layer is a continuous material layer that extends over the floating gates of the first and second memory devices and the shallow trench isolation structure. 
     
     
         3 . The NVM structure of  claim 1 , wherein the first doped well extends along opposite sides of the shallow trench isolation structure. 
     
     
         4 . The NVM structure of  claim 3 , wherein portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm. 
     
     
         5 . The NVM structure of  claim 1 , wherein the shallow trench isolation structure extends into a trench in the substrate and is at least partially surrounded by the source region. 
     
     
         6 . The NVM structure of  claim 5 , wherein the source region comprises a first doped well and a deep doped well. 
     
     
         7 . The NVM structure of  claim 5 , further comprising first and second drain regions respectively coupled to the first and second memory devices, wherein a depth of the source region is greater than a depth of the first and second drain regions. 
     
     
         8 . The NVM structure of  claim 1 , wherein an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices. 
     
     
         9 . The NVM structure of  claim 1 , wherein an upper surface of the shallow trench isolation structure is between upper and lower surfaces of the tunnelling insulators of the first and second memory devices. 
     
     
         10 . The NVM structure of  claim 1 , wherein the shallow trench isolation structure extends between sidewalls of the tunneling insulators of the first and second memory devices. 
     
     
         11 . A circuit comprising a non-volatile memory (NVM) structure, the NVM structure comprising:
 first and second memory devices on a semiconductor substrate, each of the first and second memory devices including:
 a floating gate, 
 a tunnelling insulator under the floating gate, 
 an isolation layer over the floating gate, and 
 at least one of a select gate and a control gate over the isolation layer, 
   an erase gate shared by the first and second memory devices;   a source region under the erase gate; and   a shallow trench isolation structure between the erase gate and the source region.   
     
     
         12 . The circuit of  claim 11 , further comprising a processor coupled to the NVM structure. 
     
     
         13 . The circuit of  claim 11 , wherein the isolation layer is a continuous material layer that extends over the floating gates of the first and second memory devices and the shallow trench isolation structure. 
     
     
         14 . The circuit of  claim 11 , wherein the first doped well extends along opposite sides of the shallow trench isolation structure. 
     
     
         15 . The circuit of  claim 11 , wherein the shallow trench isolation structure extends into a trench in the substrate and is at least partially surrounded by the source region. 
     
     
         16 . The circuit of  claim 15 , wherein the source region comprises a first doped well and a deep doped well. 
     
     
         17 . The circuit of  claim 15 , further comprising first and second drain regions respectively coupled to the first and second memory devices, wherein a depth of the source region is greater than a depth of the first and second drain regions. 
     
     
         18 . The circuit of  claim 11 , wherein the shallow trench isolation structure extends between sidewalls of the tunneling insulators of the first and second memory devices. 
     
     
         19 . A method of forming a non-volatile memory (NVM) structure, the method comprising:
 forming first and second memory devices on a semiconductor substrate, each of the first and second memory devices including:
 a floating gate, 
 a tunnelling insulator under the floating gate, 
 an isolation layer over the floating gate, and 
 at least one of a select gate and a control gate over the isolation layer, 
   forming a shallow trench isolation structure between the first and second memory devices;   forming a source region under the erase gate; and   forming an erase gate shared by the first and second memory devices.   
     
     
         20 . The method of  claim 19 , wherein the shallow trench isolation structure extends into a trench in the substrate and is at least partially surrounded by the source region, and wherein the source region comprises a first doped well and a deep doped well.