US2025126821A1PendingUtilityA1

FINFET Device and Method of Forming Same

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Oct 31, 2018Filed: Dec 23, 2024Published: Apr 17, 2025
Est. expiryOct 31, 2038(~12.2 yrs left)· nominal 20-yr term from priority
H10P 30/204H10P 30/22H10P 30/21H10P 72/0421H10P 70/20H10P 50/242H10W 10/17H10W 10/014H10P 72/7616H10P 72/0432H10D 64/021H10D 30/0227H10D 64/017H10D 62/405H10D 62/151H10D 62/021H10D 30/6211H01J 37/32449H01J 2237/335H01J 2237/334H01J 37/32724H01J 37/321H10D 12/038H10D 30/6219H10D 30/797H10D 62/822H10D 84/853H10D 84/038H10D 84/0193H10D 30/62H01J 2237/3346H01J 37/32431H10D 30/024H01L 21/266H01L 21/26513H01L 21/76224H01L 21/67069H01L 21/3065H01L 21/02057H10P 72/0602H10P 72/0431H10P 95/90H10P 72/0406H10P 14/6532H10P 70/12
81
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method comprising:
 forming a fin over a semiconductor substrate;   performing a plasma etching process to form a recess in the fin, wherein a bottom surface of the recess has a first depth, wherein the recess has a first width between sidewall surfaces;   performing a plasma cleaning process on surfaces of the recess, wherein the plasma cleaning process comprises exposing surfaces of the recess to hydrogen radicals, wherein the plasma cleaning process deepens and widens the recess, wherein after performing the plasma cleaning process the sidewall surfaces of the recess are convex and the bottom surface of the recess is tapered and faceted.   
     
     
         2 . The method of  claim 1 , wherein after performing the plasma cleaning process, the bottom surface of the recess is V-shaped. 
     
     
         3 . The method of  claim 1 , wherein after performing the plasma cleaning process, the bottom surface of the recess comprises ( 111 ) facets. 
     
     
         4 . The method of  claim 1 , wherein before performing the plasma cleaning process, the sidewall surfaces of the recess are flat and parallel. 
     
     
         5 . The method of  claim 1 , wherein the plasma cleaning process widens the recess by a distance in the range of 1 nm to 3 nm. 
     
     
         6 . The method of  claim 1 , wherein the plasma cleaning process removes carbon residue from the recess. 
     
     
         7 . The method of  claim 1 , wherein the plasma cleaning process deepens the recess by a distance in the range of 1 nm to 5 nm. 
     
     
         8 . The method of  claim 1 , wherein the plasma cleaning process uses different process gases than the plasma etching process. 
     
     
         9 . A method comprising:
 etching a recess in a semiconductor fin, wherein the etching comprises first process gases, wherein the recess has vertical sidewalls and a U-shaped bottom;   performing a cleaning process on the recess, wherein the cleaning process comprises second process gases, wherein the second process gases are free of halogens, wherein the cleaning process expands the volume of the recess, wherein after performing the cleaning process, the recess has curved sidewalls and a V-shaped bottom.   
     
     
         10 . The method of  claim 9 , wherein the second process gases comprise hydrogen radicals. 
     
     
         11 . The method of  claim 9  further comprising forming an epitaxial region in the recess. 
     
     
         12 . The method of  claim 9 , wherein the cleaning process selectively etches first crystalline planes of the semiconductor fin having a first crystalline orientation over second crystalline planes of the semiconductor fin having a second crystalline orientation. 
     
     
         13 . The method of  claim 12 , wherein the second crystalline orientation is ( 111 ). 
     
     
         14 . The method of  claim 9 , wherein the cleaning process comprises forming a plasma. 
     
     
         15 . The method of  claim 9 , wherein the cleaning process comprises preventing hydrogen ions from etching the semiconductor fin. 
     
     
         16 . A method comprising:
 forming a semiconductor fin protruding from a substrate;   forming a gate structure over the semiconductor fin;   forming a spacer over the semiconductor fin adjacent the gate structure;   performing an etching process to form a recess in the semiconductor fin adjacent the spacer; and   after performing the etching process, performing a plasma process on the semiconductor fin, wherein the plasma process preferentially etches ( 100 ) crystalline planes over ( 111 ) crystalline planes using hydrogen radicals, wherein after performing the plasma process a sidewall of the recess extends underneath the spacer, wherein after performing the plasma process the bottom surface of the recess comprises intersecting ( 111 ) crystalline planes.   
     
     
         17 . The method of  claim 16 , wherein the plasma process is free of halogens. 
     
     
         18 . The method of  claim 16 , wherein before performing the plasma process, the recess does not extend underneath the spacer. 
     
     
         19 . The method of  claim 16 , wherein before performing the plasma process the bottom surface of the recess is curved. 
     
     
         20 . The method of  claim 16 , wherein an angle between a ( 111 ) crystalline plane of the bottom recess and a ( 100 ) crystalline plane of silicon is in the range of 30 degrees and 90 degrees.

Join the waitlist — get patent alerts

Track US2025126821A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.