Memory and operating method thereof

Abstract

A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

What is claimed is: 
     
         1 . A device, comprising:
 a memory device configured to store a plurality of bits;   a reading device coupled to the memory device at a first node; and   a feedback device configured to adjust the reading device based on a first voltage signal generated at the first node,   wherein the first voltage signal is generated based on the plurality of bits.   
     
     
         2 . The device of  claim 1 , wherein the reading device comprises:
 a first switch coupled to the first node; and   a second switch configured to control of the first switch according to a first control signal,   wherein the feedback device is configured to generate the first control signal based on the first voltage signal.   
     
     
         3 . The device of  claim 2 , wherein the reading device further comprises:
 a third switch configured to provide a reference voltage signal to a control terminal of the first switch according to the first control signal,   the first switch is configured to provide the reference voltage signal to the first node.   
     
     
         4 . The device of  claim 2 , wherein the reading device further comprises:
 a third switch coupled to the first node; and   a fourth switch configured to control of the third switch according to a second control signal,   wherein the feedback device is configured to generate the first control signal based on the first voltage signal.   
     
     
         5 . The device of  claim 4 , wherein the feedback device comprises:
 a first logic unit configured to receive a reference voltage signal to generate the first control signal; and   a second logic unit configured to receive the reference voltage signal to generate the second control signal.   
     
     
         6 . The device of  claim 5 , wherein the reading device further comprises:
 a fifth switch configured to provide the reference voltage signal to a control terminal of the first switch according to the second control signal.   
     
     
         7 . The device of  claim 6 , wherein the second logic unit comprises:
 a first logic element configured to receive the reference voltage signal and output a third control signal; and   a second logic element configured to receive the third control signal and output the second control signal,   wherein a control terminal of the fifth switch is configured to receive the third control signal.   
     
     
         8 . The device of  claim 6 , wherein each of the third switch and the fifth switch has a first conductive type, and
 the first switch has a second conductive type different from the first conductive type.   
     
     
         9 . A device, comprising:
 a memory device;   a first reading circuit coupled to the memory device, and configured to generate a first voltage signal based on data stored in the memory device; and   a feedback device configured to adjust the first reading circuit based on the first voltage signal.   
     
     
         10 . The device of  claim 9 , further comprising:
 a sensing device configured to generate a first digital signal according to the first voltage signal,   wherein a bit value of the first digital signal is same as a most significant bit of the data.   
     
     
         11 . The device of  claim 9 , further comprising:
 a second reading circuit coupled between the first reading circuit and the memory device, and configured to generate the first voltage signal with the first reading circuit,   wherein the feedback device is further configured to adjust the second reading circuit based on the first voltage signal.   
     
     
         12 . The device of  claim 11 , further comprising:
 a sensing device configured to generate a first digital signal and a second digital signal according to the first voltage signal,   wherein the feedback device is configured to generate a first control signal and a second control signal based on the first digital signal and the second digital signal, respectively,   the first reading circuit and the second reading circuit are configured to receive the first control signal and the second control signal, respectively.   
     
     
         13 . The device of  claim 12 , wherein the first digital signal and the second digital signal are complemented from each other. 
     
     
         14 . The device of  claim 12 , wherein the feedback device comprises:
 a first logic unit configured to receive a reference voltage signal and the first digital signal and output the first control signal; and   a second logic unit configured to receive the reference voltage signal and the second digital signal and output the second control signal.   
     
     
         15 . The device of  claim 14 , wherein each of the memory device and the second reading circuit is configured to receive the reference voltage signal. 
     
     
         16 . A method, comprising:
 generating a first voltage signal at a first node according to data;   generating a first control signal based on the first voltage signal;   receiving the first control signal by a reading device; and   generating, corresponding to the data, a second voltage signal at the first node by the reading device.   
     
     
         17 . The method of  claim 16 , further comprising:
 providing a first reference voltage signal to a second node according to the by a first switch; and   providing the first reference voltage signal to the first node by a second switch,   wherein a control terminal of the second switch is coupled to the second node.   
     
     
         18 . The method of  claim 17 , further comprising:
 generating a second control signal based on the first voltage signal;   inverting the second control signal to generate the first control signal;   receiving each of the second control signal and the first control signal by a third switch; and   controlling the second switch by the third switch.   
     
     
         19 . The method of  claim 17 , further comprising:
 providing a second reference voltage signal to a third node according to the by a third switch;   storing the data by a memory device; and   coupling the memory device to the first node by a fourth switch,   wherein a control terminal of the fourth switch is coupled to the third node.   
     
     
         20 . The method of  claim 19 , wherein generating the first control signal comprises:
 generating the first control signal based on the second reference voltage signal.