Instructions to convert from fp16 to bf8

Abstract

Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

1 - 20 . (canceled) 
     
     
         21 . An apparatus comprising:
 decoder circuitry to decode a single instruction, the single instruction having a first field to identify a first source single instruction, multiple data (SIMD) register, a second field to identify a second source SIMD register, and a third field to identify a destination SIMD register, the first source SIMD register to store a first plurality of half-precision floating-point data elements, the second source SIMD register to store a second plurality of half-precision floating-point data elements; and   execution circuitry to perform operations corresponding to the single instruction, including to:
 convert the first plurality of half-precision floating-point data elements to a first plurality of 8-bit floating-point data elements; 
 convert the second plurality of half-precision floating-point data elements to a second plurality of 8-bit floating-point data elements; and 
 store the first and second pluralities of 8-bit floating-point data elements in corresponding data element positions of the destination SIMD register. 
   
     
     
         22 . The apparatus of  claim 21 , wherein the execution circuitry is to store the second plurality of 8-bit floating-point data elements in most significant data element positions of the destination SIMD register. 
     
     
         23 . The apparatus of  claim 22 , wherein the execution circuitry is to store the first plurality of 8-bit floating-point data elements in least significant data element positions of the destination SIMD register. 
     
     
         24 . The apparatus of  claim 21 , wherein the first plurality of 8-bit floating-point data elements have a format comprising a 1-bit sign, a 5-bit exponent, and a 2-bit mantissa. 
     
     
         25 . The apparatus of  claim 21 , wherein the execution circuitry is to convert a half-precision floating-point data element of the first plurality of half-precision floating-point data elements to an 8-bit floating-point data element of the first plurality of 8-bit floating-point data elements based on a value in a register. 
     
     
         26 . The apparatus of  claim 25 , wherein the value is an 8-bit value in the register. 
     
     
         27 . The apparatus of  claim 21 , wherein the execution circuitry is to convert the first plurality of half-precision floating-point data elements to corresponding ones of the first plurality of 8-bit floating-point data elements, and convert the second plurality of half-precision floating-point data elements to corresponding ones of the second plurality of 8-bit floating-point data elements, using an associated value from a register. 
     
     
         28 . The apparatus of  claim 21 , wherein the execution circuitry is to convert the first and second pluralities of half-precision floating-point data elements to the first and second pluralities of 8-bit floating-point data elements based on a plurality of values in a source register, wherein a first value of the plurality of values in the source register is to bias rounding of a first half-precision floating-point data element of the first plurality of half-precision floating-point data elements. 
     
     
         29 . The apparatus of  claim 21 , wherein the first and second source SIMD registers are 128-bit registers, and wherein the destination SIMD register is a 128-bit register. 
     
     
         30 . The apparatus of  claim 21 , wherein the first and second source SIMD registers are 64-bit registers, and wherein the destination SIMD register is a 64-bit register. 
     
     
         31 . The apparatus of  claim 21 , wherein the execution circuitry is to convert a half-precision floating-point data element of the first plurality of half-precision floating-point data elements to an 8-bit floating-point data element of the first plurality of 8-bit floating-point data elements based on a value in a register, wherein the execution circuitry is to store the second plurality of 8-bit floating-point data elements in most significant data element positions of the destination SIMD register, wherein the execution circuitry is to store the first plurality of 8-bit floating-point data elements in least significant data element positions of the destination SIMD register, wherein the first plurality of 8-bit floating-point data elements have a format comprising a 1-bit sign, a 5-bit exponent, and a 2-bit mantissa, and wherein the first and second source SIMD registers are 128-bit registers, and wherein the destination SIMD register is a 128-bit register. 
     
     
         32 . The apparatus of  claim 21 , wherein the execution circuitry is to convert the first and second pluralities of half-precision floating-point data elements to the first and second pluralities of 8-bit floating-point data elements based on a plurality of values in a source register, wherein a first value of the plurality of values in the source register is to bias rounding of a first half-precision floating-point data element of the first plurality of half-precision floating-point data elements, wherein the execution circuitry is to store the second plurality of 8-bit floating-point data elements in most significant data element positions of the destination SIMD register, wherein the execution circuitry is to store the first plurality of 8-bit floating-point data elements in least significant data element positions of the destination SIMD register, wherein the first plurality of 8-bit floating-point data elements have a format comprising a 1-bit sign, a 5-bit exponent, and a 2-bit mantissa, and wherein the first and second source SIMD registers are 128-bit registers, and wherein the destination SIMD register is a 128-bit register. 
     
     
         33 . A method comprising:
 decoding a single instruction, the single instruction having a first field identifying a first source single instruction, multiple data (SIMD) register, a second field identifying a second source SIMD register, and a third field identifying a destination SIMD register, the first source SIMD register storing a first plurality of half-precision floating-point data elements, the second source SIMD register storing a second plurality of half-precision floating-point data elements; and   performing operations corresponding to the single instruction, including:
 converting the first plurality of half-precision floating-point data elements to a first plurality of 8-bit floating-point data elements; 
 converting the second plurality of half-precision floating-point data elements to a second plurality of 8-bit floating-point data elements; and 
 storing the first and second pluralities of 8-bit floating-point data elements in corresponding data element positions of the destination SIMD register. 
   
     
     
         34 . The method of  claim 33 , wherein the second plurality of 8-bit floating-point data elements are stored in most significant data element positions of the destination SIMD register, wherein the first plurality of 8-bit floating-point data elements are stored in least significant data element positions of the destination SIMD register, and wherein the first plurality of 8-bit floating-point data elements have a format comprising a 1-bit sign, a 5-bit exponent, and a 2-bit mantissa. 
     
     
         35 . The method of  claim 33 , wherein a half-precision floating-point data element of the first plurality of half-precision floating-point data elements is converted to an 8-bit floating-point data element of the first plurality of 8-bit floating-point data elements based on a value in a register. 
     
     
         36 . The method of  claim 35 , wherein the value is an 8-bit value in the register. 
     
     
         37 . The method of  claim 33 , wherein the first plurality of half-precision floating-point data elements are converted to corresponding ones of the first plurality of 8-bit floating-point data elements, and the second plurality of half-precision floating-point data elements are converted to corresponding ones of the second plurality of 8-bit floating-point data elements, using an associated value from a register. 
     
     
         38 . The method of  claim 33 , wherein the first and second pluralities of half-precision floating-point data elements are respectively converted to the first and second pluralities of 8-bit floating-point data elements based on a plurality of values in a source register, wherein a first value of the plurality of values in the source register biases rounding of a first half-precision floating-point data element of the first plurality of half-precision floating-point data elements. 
     
     
         39 . The method of  claim 33 , wherein the first and second source SIMD registers are 128-bit registers, and wherein the destination SIMD register is a 128-bit register. 
     
     
         40 . A system comprising:
 a dynamic random access memory (DRAM); and   a processor coupled with the DRAM, the processor comprising:
 decoder circuitry to decode a single instruction, the single instruction having a first field to identify a first source single instruction, multiple data (SIMD) register, a second field to identify a second source SIMD register, and a third field to identify a destination SIMD register, the first source SIMD register to store a first plurality of half-precision floating-point data elements, the second source SIMD register to store a second plurality of half-precision floating-point data elements; and 
 execution circuitry to perform operations corresponding to the single instruction, including to:
 convert the first plurality of half-precision floating-point data elements to a first plurality of  8 -bit floating-point data elements; 
 convert the second plurality of half-precision floating-point data elements to a second plurality of 8-bit floating-point data elements; and 
 store the first and second pluralities of 8-bit floating-point data elements in corresponding data element positions of the destination SIMD register. 
 
   
     
     
         41 . The system of  claim 40 , further comprising a mass storage device coupled with the DRAM, wherein the execution circuitry is to store the second plurality of 8-bit floating-point data elements in most significant data element positions of the destination SIMD register, and wherein the execution circuitry is to store the first plurality of 8-bit floating-point data elements in least significant data element positions of the destination SIMD register, and wherein the first plurality of 8-bit floating-point data elements have a format comprising a 1-bit sign, a 5-bit exponent, and a 2-bit mantissa. 
     
     
         42 . The system of  claim 40 , further comprising a communication device coupled with the processor, wherein the execution circuitry is to convert the first plurality of half-precision floating-point data elements to corresponding ones of the first plurality of 8-bit floating-point data elements, and convert the second plurality of half-precision floating-point data elements to corresponding ones of the second plurality of 8-bit floating-point data elements, using an associated value from a register. 
     
     
         43 . The system of  claim 40 , further comprising a graphics processing unit coupled with the processor, wherein the first and second source SIMD registers are 128-bit registers, and wherein the destination SIMD register is a 128-bit register, and wherein the execution circuitry is to convert the first and second pluralities of half-precision floating-point data elements to the first and second pluralities of 8-bit floating-point data elements based on a plurality of values in a source register, wherein a first value of the plurality of values in the source register is to bias rounding of a first half-precision floating-point data element of the first plurality of half-precision floating-point data elements.