Carbon nanotube devices

Abstract

A method includes forming, on a dielectric layer of an integrated circuit, a first layer of a first material, forming, on the first layer, a second layer of a second material, and patterning the second layer to expose the first layer. Via the patterned second layer, the exposed first layer is etched to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures. The method also includes forming a graphitic carbon layer on at least part of the second layer of the protrusion structures, and depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.

What is claimed is: 
     
         1 . A method comprising:
 forming, on a dielectric layer of an integrated circuit, a first layer of a first material;   forming, on the first layer, a second layer of a second material;   patterning the second layer to expose the first layer;   via the patterned second layer, etching the exposed first layer to form protrusion structures of the first layer and the second layer and undercut grooves between adjacent ones of the protrusion structures, in which the first layer of each protrusion structure has a first width, the second layer of each protrusion structure has a second width, and the second width is greater than the first width; and   depositing carbon nanotubes into the undercut grooves between the adjacent ones of the protrusion structures.   
     
     
         2 . The method of  claim 1 , further comprising forming a graphitic carbon layer on the patterned second layer and before depositing the carbon nanotubes. 
     
     
         3 . The method of  claim 1 , further comprising removing the protrusion structures after depositing the carbon nanotubes. 
     
     
         4 . The method of  claim 1 , further comprising forming a dielectric layer on the carbon nanotubes. 
     
     
         5 . The method of  claim 1 , further comprising longitudinally aligning the carbon nanotubes with the protrusion structures. 
     
     
         6 . The method of  claim 1 , wherein the first material includes aluminum or a dielectric material. 
     
     
         7 . The method of  claim 1 , wherein the second material includes at least one of: nickel, cobalt, copper, palladium, ruthenium, platinum, or binary alloys thereof. 
     
     
         8 . The method of  claim 1 , wherein the first width is less than a minimum line width of the patterned second layer. 
     
     
         9 . A method comprising:
 forming, on a dielectric layer of an integrated circuit, a first layer of a first material;   forming, on the first layer, a second layer of a second material;   patterning the second layer to expose the first layer;   via the patterned second layer, etching the exposed second layer to form protrusion structures of the first layer and the second layer and grooves between adjacent ones of the protrusion structures; and   forming a graphitic carbon layer on at least part of the second layer of the protrusion structures; and   depositing carbon nanotubes into the grooves between the adjacent ones of the protrusion structures.   
     
     
         10 . The method of  claim 9 , wherein the first layer of each protrusion structure has a first width, the second layer of each protrusion structure has a second width, and the second width is greater than the first width. 
     
     
         11 . The method of  claim 10 , wherein the first width is less than a minimum line width. 
     
     
         12 . The method of  claim 9 , further comprising removing the protrusion structures after depositing the carbon nanotubes. 
     
     
         13 . The method of  claim 9 , further comprising forming a dielectric layer on the carbon nanotubes. 
     
     
         14 . The method of  claim 9 , further comprising longitudinally aligning the carbon nanotubes with the protrusion structures. 
     
     
         15 . The method of  claim 9 , wherein the first material includes aluminum or a dielectric material. 
     
     
         16 . The method of  claim 9 , wherein the second material includes at least one of: nickel, cobalt, copper, palladium, ruthenium, platinum, or binary alloys thereof. 
     
     
         17 . A transistor comprising:
 a source and a drain;   a first array of carbon nanotubes having a first width, a first end connected to the source, and a second end connected to the drain; and   a second array of carbon nanotubes adjacent to and spaced apart from the first array of carbon nanotubes by a first spacing;   wherein the first width is greater than the first spacing.   
     
     
         18 . The transistor of  claim 17 , wherein the first width is at least twice the first spacing. 
     
     
         19 . The transistor of  claim 17 , further comprising a gate disposed beneath the first array of carbon nanotubes. 
     
     
         20 . The transistor of  claim 17 , further comprising an insulation layer over the first and second arrays of carbon nanotubes.