Semiconductor structure and manufacturing method thereof

Abstract

A method includes forming first, second, third, and fourth semiconductive sheets over a substrate and arranged in a vertical direction; forming a first source/drain region between the first and second semiconductive sheets, and a second source/drain region between the third and fourth semiconductive sheets; forming a first gate around each of the first semiconductive sheets, a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets, wherein the second gate pitch of the third and fourth gates is greater than the first gate pitch of the first and second gates; forming first spacers interleaving with the first semiconductive sheets, and second spacers interleaving with the third semiconductive sheets, wherein the second lateral dimension of the second spacers is greater than the first lateral dimension of the first spacers.

What is claimed is: 
     
         1 . A method, comprising:
 forming first semiconductive sheets over a substrate and arranged in a vertical direction, second semiconductive sheets over the substrate and arranged in the vertical direction, third semiconductive sheets over the substrate and arranged in the vertical direction, and fourth semiconductive sheets over the substrate and arranged in the vertical direction;   forming a first source/drain region between the first semiconductive sheets and the second semiconductive sheets, and a second source/drain region between the third semiconductive sheets and the second semiconductive sheets;   forming a first gate around each of the first semiconductive sheets, a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets,   wherein the first and second gates has a first gate pitch therebetween, the third and fourth gates has a second gate pitch therebetween, and the second gate pitch is greater than the first gate pitch; and   forming first spacers interleaving with the first semiconductive sheets and between the first gate and the first source/drain region, and second spacers interleaving with the third semiconductive sheets and between the third gate and the second source/drain region, wherein the first spacers each has a first lateral dimension in a lengthwise direction of one of the first semiconductive sheets, the second spacers each has a second lateral dimension in the lengthwise direction of the one of the first semiconductive sheets, and the second lateral dimension is greater than the first lateral dimension.   
     
     
         2 . The method of  claim 1 , wherein a gate pitch ratio of the second gate pitch to the first gate pitch is greater than about 1.1. 
     
     
         3 . The method of  claim 1 , wherein a ratio of the second lateral dimension of the second spacers to the first lateral dimension of the first spacers is greater than about 1.05. 
     
     
         4 . The method of  claim 1 , wherein the first, second, third, and fourth gates each comprises a gate dielectric layer and a gate electrode layer over the gate dielectric layer, and the gate dielectric layer of the first gate, the gate dielectric layer of the second gate, the gate dielectric layer of the third gate, the gate dielectric layer of the fourth gate have a same thickness as each other. 
     
     
         5 . The method of  claim 4 , wherein the gate electrode layer of the first gate and the gate electrode layer of the second gate have a first distance therebetween, the gate electrode layer of the third gate and the gate electrode layer of the fourth gate have a second distance therebetween, and the second distance is greater than the first distance. 
     
     
         6 . The method of  claim 5 , wherein a ratio of the second distance to the first distance is greater than about 1.1. 
     
     
         7 . The method of  claim 5 , wherein the gate electrode layer of the first gate has a first gate length, the gate electrode layer of the third gate has a second gate length, and the second gate length is longer than the first gate length. 
     
     
         8 . The method of  claim 7 , wherein a gate length ratio of the second gate length to the first gate length is greater than about 1.1. 
     
     
         9 . The method of  claim 7 , wherein the first gate length is in a range from about 8-20 nm, and the second gate length is in a range from about 8-16 nm. 
     
     
         10 . The method of  claim 1 , wherein the first and second semiconductive sheets, the first and second gates, and the first source/drain region are of a core device, and the third and fourth semiconductive sheets, the third and fourth gates, and the second source/drain region are of a device for a capacitor or being of an e-fuse or an analog circuit. 
     
     
         11 . A method, comprising:
 forming a first device over a substrate, the first device being of a core device, and comprising:
 a first channel pattern; 
 a first gate pattern wrapping around the first channel pattern; 
 first epitaxial patterns on either side of the first channel pattern; and 
 a first inner spacer below the first channel pattern and laterally sandwiched between the first gate pattern and one of the first epitaxial patterns; and 
   forming a second device over the substrate, the second device being of an non-core device, and comprising:
 a second channel pattern; 
 a second gate pattern wrapping around the second channel pattern, wherein the first gate pattern has a first gate length, the second gate pattern has a second gate length, the second gate length is longer than the first gate length; 
 second epitaxial patterns on either side of the second channel pattern; and 
 a second inner spacer below the second channel pattern and laterally sandwiched between the second gate pattern and one of the second epitaxial patterns, wherein the second inner spacer has a greater lateral dimension than the first inner spacer in a lengthwise direction of the first channel pattern. 
   
     
     
         12 . The method of  claim 11 , wherein the first device comprises a first top spacer over the first channel pattern and on a sidewall of the first gate pattern, the second device comprises a second top spacer over the first channel pattern and on a sidewall of the second gate pattern, and the second top spacer has a thicker thickness than the first top spacer. 
     
     
         13 . The method of  claim 12 , wherein the second top spacer is thicker than the first top spacer in a range from about 0.5 to 5 nm. 
     
     
         14 . The method of  claim 12 , further comprising:
 forming a contact over one of the first epitaxial patterns, the contact being in contact with the first top spacer.   
     
     
         15 . The method of  claim 12 , further comprising:
 forming a contact over one of the second epitaxial patterns, the contact being spaced apart from the second top spacer.   
     
     
         16 . A semiconductor structure, comprising:
 a substrate;   a first transistor over a substrate, the first transistor comprising:
 first nanostructures arranged in a vertical direction; 
 first epitaxial structures on either side of each of the first nanostructures; and 
 a first gate structure around the first nanostructures and between the first epitaxial structures; 
   a first dielectric spacer over the first nanostructures and on a sidewall of the first gate structure; and   second dielectric spacers interleaving with the first nanostructures and between the first gate structure and one of the first epitaxial structures, wherein each of the second dielectric spacers has a greater lateral dimension than the first dielectric spacer in a lengthwise direction of one of the first nanostructures.   
     
     
         17 . The semiconductor structure of  claim 16 , further comprising:
 a second transistor over the substrate, the first transistor comprising:
 second nanostructures arranged in the vertical direction; 
 second epitaxial structures on either side of each of the second nanostructures; and 
 a second gate structure around the second nanostructures and between the second epitaxial structures; and 
   third dielectric spacers interleaving with the second nanostructures and between the second gate structure and one of the second epitaxial structures, wherein each of the second dielectric spacers has a greater lateral dimension than the third dielectric spacers in the lengthwise direction of the one of the first nanostructures.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the first transistor is of a core device, and the second transistor is of a device for a capacitor or being of an e-fuse or an analog circuit. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein the first gate structure has a first gate length, the second gate structure has a second gate length, and the first gate length is longer than the second gate length. 
     
     
         20 . The semiconductor structure of  claim 16 , further comprising:
 a dielectric layer between one of the first epitaxial structures and the substrate.