Microarchitecture and instruction set architecture extensions for efficient iso-area victim buffering through translation lookaside buffer partitioning

Abstract

Techniques for victim buffering through translation lookaside buffer (TLB) partitioning are described. In certain examples, a system includes a memory; an execution circuitry to generate a memory access request for a virtual memory address of the memory; a first level translation lookaside buffer to store virtual address to physical address mappings; a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer; a second level translation lookaside buffer; and a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.

What is claimed is: 
     
         1 . An apparatus comprising:
 an execution circuitry to generate a memory access request for a virtual memory address;   a first level translation lookaside buffer to store virtual address to physical address mappings;   a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer;   a second level translation lookaside buffer; and   a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         2 . The apparatus of  claim 1 , wherein the cache coherency circuitry is to simultaneously search the first level translation lookaside buffer and the victim translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request. 
     
     
         3 . The apparatus of  claim 1 , wherein the cache coherency circuitry is to, for the miss in the first level translation lookaside buffer and the victim translation lookaside buffer:
 cause a page walk to determine the corresponding physical address mapped to the virtual memory address for the memory access request;   determine a victim entry in the first level translation lookaside buffer;   fill the victim entry into the victim translation lookaside buffer; and   replace the victim entry in the first level translation lookaside buffer with an entry from the page walk for the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         4 . The apparatus of  claim 3 , wherein the victim entry in the first level translation lookaside buffer comprises a victim translation lookaside buffer hint bit, and the cache coherency circuitry is to, in response to the victim translation lookaside buffer hint bit being set, fill the victim entry into the victim translation lookaside buffer, and in response to the victim translation lookaside buffer hint bit not being set, not fill the victim entry into the victim translation lookaside buffer. 
     
     
         5 . The apparatus of  claim 4 , further comprising a decoder circuitry to decode an instruction into a decoded instruction, wherein the execution circuitry is to execute the decoded instruction to set the victim translation lookaside buffer hint bit in an entry in the first level translation lookaside buffer before a determination that the entry is the victim entry in the first level translation lookaside buffer. 
     
     
         6 . The apparatus of  claim 1 , wherein a set indexer for the first level translation lookaside buffer is different than a set indexer for the victim translation lookaside buffer. 
     
     
         7 . The apparatus of  claim 1 , wherein the first level translation lookaside buffer has more entries than the victim translation lookaside buffer. 
     
     
         8 . A method comprising:
 generating, by an execution circuitry, a memory access request for a virtual memory address of a memory;   storing virtual address to physical address mappings in a first level translation lookaside buffer;   storing, in a victim translation lookaside buffer, a virtual address to physical address mapping evicted from the first level translation lookaside buffer; and   searching, by a cache coherency circuitry, the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, searching a second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, providing the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         9 . The method of  claim 8 , wherein the searching is simultaneously searching the first level translation lookaside buffer and the victim translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request. 
     
     
         10 . The method of  claim 8 , further comprising, in response to the miss in the first level translation lookaside buffer and the victim translation lookaside buffer:
 performing a page walk to determine the corresponding physical address mapped to the virtual memory address for the memory access request;   determining a victim entry in the first level translation lookaside buffer;   filling the victim entry into the victim translation lookaside buffer; and   replacing the victim entry in the first level translation lookaside buffer with an entry from the page walk for the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         11 . The method of  claim 10 , wherein the victim entry in the first level translation lookaside buffer comprises a victim translation lookaside buffer hint bit, and in response to the victim translation lookaside buffer hint bit being set, filling the victim entry into the victim translation lookaside buffer, and in response to the victim translation lookaside buffer hint bit not being set, not filling the victim entry into the victim translation lookaside buffer. 
     
     
         12 . The method of  claim 11 , further comprising:
 decoding, by decoder circuitry, an instruction into a decoded instruction; and   executing, by the execution circuitry, the decoded instruction to set the victim translation lookaside buffer hint bit in an entry in the first level translation lookaside buffer before a determination that the entry is the victim entry in the first level translation lookaside buffer.   
     
     
         13 . The method of  claim 8 , wherein a set indexer for the first level translation lookaside buffer is different than a set indexer for the victim translation lookaside buffer. 
     
     
         14 . The method of  claim 8 , wherein the first level translation lookaside buffer has more entries than the victim translation lookaside buffer. 
     
     
         15 . A system comprising:
 a memory;   an execution circuitry to generate a memory access request for a virtual memory address of the memory;   a first level translation lookaside buffer to store virtual address to physical address mappings;   a victim translation lookaside buffer to store a virtual address to physical address mapping evicted from the first level translation lookaside buffer;   a second level translation lookaside buffer; and   a cache coherency circuitry to search the first level translation lookaside buffer and the victim translation lookaside buffer for a corresponding physical address mapped to the virtual memory address for the memory access request, and for a miss in the first level translation lookaside buffer and the victim translation lookaside buffer, search the second level translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request, and for a hit in the victim translation lookaside buffer, provide the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         16 . The system of  claim 15 , wherein the cache coherency circuitry is to simultaneously search the first level translation lookaside buffer and the victim translation lookaside buffer for the corresponding physical address mapped to the virtual memory address for the memory access request. 
     
     
         17 . The system of  claim 15 , wherein the cache coherency circuitry is to, for the miss in the first level translation lookaside buffer and the victim translation lookaside buffer:
 cause a page walk of the memory to determine the corresponding physical address mapped to the virtual memory address for the memory access request;   determine a victim entry in the first level translation lookaside buffer;   fill the victim entry into the victim translation lookaside buffer; and   replace the victim entry in the first level translation lookaside buffer with an entry from the page walk for the corresponding physical address mapped to the virtual memory address for the memory access request.   
     
     
         18 . The system of  claim 17 , wherein the victim entry in the first level translation lookaside buffer comprises a victim translation lookaside buffer hint bit, and the cache coherency circuitry is to, in response to the victim translation lookaside buffer hint bit being set, fill the victim entry into the victim translation lookaside buffer, and in response to the victim translation lookaside buffer hint bit not being set, not fill the victim entry into the victim translation lookaside buffer. 
     
     
         19 . The system of  claim 18 , further comprising a decoder circuitry to decode an instruction into a decoded instruction, wherein the execution circuitry is to execute the decoded instruction to set the victim translation lookaside buffer hint bit in an entry in the first level translation lookaside buffer before a determination that the entry is the victim entry in the first level translation lookaside buffer. 
     
     
         20 . The system of  claim 15 , wherein a set indexer for the first level translation lookaside buffer is different than a set indexer for the victim translation lookaside buffer.