US2025098322A1PendingUtilityA1

Metal insulator metal capacitor (mim capacitor)

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Assignee: IBMPriority: Sep 14, 2023Filed: Sep 14, 2023Published: Mar 20, 2025
Est. expirySep 14, 2043(~17.1 yrs left)· nominal 20-yr term from priority
Inventors:Huimei ZhouShahrukh KhanBaozhen LiRuilong XieYoo-Mi LeeChih-Chao Yang
H10D 1/692B82Y 10/00H10D 30/501H10D 1/68H10D 30/6735H10D 30/6757H10D 86/421H10D 87/00H10D 86/481H10D 86/0214H10D 86/60H10D 86/01H10D 86/80
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Claims

Abstract

A semiconductor device including a first stacked nanosheet Field Effect Transistor (FET), a second stacked nanosheet, a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet and an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet. An embodiment where the first stacked nanosheet and the second stacked nanosheet each include an upper stacked nanosheet and a lower stacked nanosheet, the upper stacked nanosheet and the lower stacked nanosheet each include alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another. Forming a first stacked nanosheet, forming a second stacked nanosheet, forming a MIM capacitor between the first stacked nanosheet and the second stacked nanosheet and forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first stacked nanosheet Field Effect Transistor (FET);   a second stacked nanosheet;   a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet; and   an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a backside contact below the second stacked nanosheet connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the first stacked FET comprises a replacement gate. 
     
     
         4 . The semiconductor device according to  claim 1 , further comprising:
 a second electrode of the MIM capacitor connected to an inner plate of the MIM capacitor.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first stacked nanosheet and the second stacked nanosheet each comprise:
 an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise:   alternating layers of a work function metal and a semiconductor channel material vertically aligned and stacked one on top of another.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein the MIM capacitor comprises an outer plate, a MIM insulator and an inner plate. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein a height of the MIM capacitor is greater than a height of the first stacked nanosheet. 
     
     
         8 . A semiconductor device comprising:
 a first stacked nanosheet;   a second stacked nanosheet;   a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet; and   an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet,   wherein the first stacked nanosheet and the second stacked nanosheet each comprise:   an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise:   alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another.   
     
     
         9 . The semiconductor device according to  claim 8 , further comprising:
 a backside contact below the second stacked nanosheet electrically connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein the first stacked FET comprises a replacement gate. 
     
     
         11 . The semiconductor device according to  claim 8 , further comprising:
 a second electrode of the MIM capacitor connected to an inner plate of the MIM capacitor.   
     
     
         12 . The semiconductor device according to  claim 8 , wherein the MIM capacitor comprises an outer plate, a MIM insulator and an inner plate. 
     
     
         13 . The semiconductor device according to  claim 8 , wherein a height of the MIM capacitor is greater than a height of the first stacked nanosheet. 
     
     
         14 . A method of forming a semiconductor device comprising:
 forming a first stacked nanosheet;   forming a second stacked nanosheet;   forming a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet; and   forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.   
     
     
         15 . The method according to  claim 14 , further comprising:
 forming a backside contact below the second stacked nanosheet electrically connecting a first electrode of the MIM capacitor and a lower source drain of the second stacked nanosheet.   
     
     
         16 . The method according to  claim 14 , wherein the first stacked FET comprises a replacement gate. 16 . The method according to  claim 13 , further comprising:
 a second electrode of the MIM capacitor connected to an inner plate of the MIM capacitor.   
     
     
         17 . The method according to  claim 14 , wherein the first stacked nanosheet and the second stacked nanosheet each comprise:
 an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise:   alternating layers of a work function metal and a semiconductor channel material vertically aligned and stacked one on top of another.   
     
     
         18 . The method according to  claim 14 , wherein the MIM capacitor comprises an outer plate, a MIM insulator and an inner plate. 
     
     
         19 . The method according to  claim 14 , wherein a height of the MIM capacitor is greater than a height of the first stacked nanosheet. 
     
     
         20 . The method according to  claim 14 , wherein the first stacked nanosheet and the second stacked nanosheet each comprise:
 an upper stacked nanosheet and a lower stacked nanosheet, wherein the upper stacked nanosheet and the lower stacked nanosheet each comprise:   alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another.

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