Array substrate, manufacturing method thereof, and display panel

Abstract

An array substrate, its manufacturing method, and a display panel are provided. The array substrate includes a substrate, a first active layer, a source-drain layer, a first gate, a second active layer, and a second gate. The first active layer includes a first channel portion corresponding to the first gate. The second active layer includes a second channel portion corresponding to the second gate. The first active layer and the second active layer are connected in parallel. The source-drain layer and the first channel portion are arranged on the surface of a same layer, so an insulating layer between the source-drain layer and the first active layer is omitted. Additionally, the first active layer directly contacts a source contact portion and a drain contact portion of the source-drain layer, so contact holes between the first active layer and the source-drain layer are omitted, simplifying fabrication of the array substrate.

What is claimed is: 
     
         1 . An array substrate, comprising:
 a substrate;   a first active layer disposed on the substrate and comprising a first channel portion;   a source-drain layer disposed on the substrate, wherein the source-drain layer and the first channel portion are disposed on a surface of a same layer, and the source-drain layer comprises a source contact portion and a drain contact portion separated from each other;   a first gate disposed on one side of the first active layer away from the substrate, wherein the first gate is disposed corresponding to the first channel portion;   a second active layer disposed on one side of the first gate away from the substrate, wherein the second active layer comprises a second channel portion, and the first channel portion and the second channel portion are separated from each other; and   a second gate disposed on one side of the second active layer away from the substrate, wherein the second gate is disposed corresponding to the second channel portion;   wherein the first active layer and the second active layer are connected in parallel, and the first active layer directly contacts the source contact portion and the drain contact portion.   
     
     
         2 . The array substrate according to  claim 1 , wherein the first active layer comprises two first doped portions disposed on two sides of the first channel portion; the second active layer comprises two second doped portions disposed on two sides of the second channel portion; the first channel portion is disposed between the source contact portion and the drain contact portion; the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively; and the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes. 
     
     
         3 . The array substrate according to  claim 2 , wherein an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion. 
     
     
         4 . The array substrate according to  claim 3 , wherein a length of the first channel portion is greater than a length of the second channel portion. 
     
     
         5 . The array substrate according to  claim 2 , further comprising a pixel electrode, wherein the pixel electrode and the second gate are disposed on a surface of a same layer, and wherein the pixel electrode is electrically connected to the first doped portion on the drain contact portion through a second via hole. 
     
     
         6 . The array substrate according to  claim 5 , wherein in a direction from the source contact portion to the drain contact portion, a width of the source contact portion is less than a width of the drain contact portion. 
     
     
         7 . The array substrate according to  claim 5 , wherein the source-drain layer further comprises a first connection terminal and a second connection terminal, and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the first channel portion; and
 the array substrate further comprises a third via hole arranged corresponding to the first connection terminal, and one end of the pixel electrode extends into the third via hole and is electrically connected to the first connection terminal.   
     
     
         8 . The array substrate according to  claim 2 , wherein the source-drain layer further comprises a first connection terminal and a second connection terminal, and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the first channel portion; and
 the source-drain layer further comprises an electrical connecting component disposed between the drain contact portion and the first connection terminal, and the drain contact portion and the first connection terminal are electrically connected through the electrical connecting component.   
     
     
         9 . The array substrate according to  claim 2 , wherein in a direction from the source contact portion to the drain contact portion, a length of the first channel portion is less than or equal to a width of the first gate. 
     
     
         10 . A display panel, comprising the array substrate as claimed in  claim 1  and a light-emitting component disposed on one side of the array substrate, wherein the array substrate and the light-emitting component are combined into a single unit. 
     
     
         11 . The display panel according to  claim 10 , wherein the first active layer comprises two first doped portions disposed on two sides of the first channel portion; the second active layer comprises two second doped portions disposed on two sides of the second channel portion; the first channel portion is disposed between the source contact portion and the drain contact portion; the two first doped portions make electrical contact with the source contact portion and the drain contact portion, respectively; and the second doped portions are electrically connected to the respectively corresponding first doped portions through first via holes. 
     
     
         12 . The display panel according to  claim 11 , wherein an ion concentration of the first doped portion is greater than an ion concentration of the second doped portion. 
     
     
         13 . The display panel according to  claim 12 , wherein a length of the first channel portion is greater than a length of the second channel portion. 
     
     
         14 . The display panel according to  claim 11 , further comprising a pixel electrode, wherein the pixel electrode and the second gate are disposed on a surface of a same layer, and wherein the pixel electrode is electrically connected to the first doped portion on the drain contact portion through a second via hole. 
     
     
         15 . The display panel according to  claim 14 , wherein in a direction from the source contact portion to the drain contact portion, a width of the source contact portion is less than a width of the drain contact portion. 
     
     
         16 . The display panel according to  claim 14 , wherein the source-drain layer further comprises a first connection terminal and a second connection terminal, and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the first channel portion; and
 the array substrate further comprises a third via hole arranged corresponding to the first connection terminal, and one end of the pixel electrode extends into the third via hole and is electrically connected to the first connection terminal.   
     
     
         17 . The display panel according to  claim 11 , wherein the source-drain layer further comprises a first connection terminal and a second connection terminal, and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the first channel portion; and
 the source-drain layer further comprises an electrical connecting component disposed between the drain contact portion and the first connection terminal, and the drain contact portion and the first connection terminal are electrically connected through the electrical connecting component.   
     
     
         18 . The display panel according to  claim 11 , wherein in a direction from the source contact portion to the drain contact portion, a length of the first channel portion is less than or equal to a width of the first gate. 
     
     
         19 . A manufacturing method of an array substrate, comprising following steps:
 S 10 : providing a substrate;   S 20 : forming a source-drain layer on the substrate;   S 30 : forming a first active layer on the substrate;   S 40 : sequentially forming a first gate insulating layer and a first gate on the first active layer;   S 50 : forming an interlayer insulating layer on the first gate;   S 60 : forming a second active layer on the interlayer insulating layer;   S 70 : forming a second gate insulating layer on the second active layer; and   S 80 : forming a second gate and a pixel electrode on the second gate insulating layer.   
     
     
         20 . The manufacturing method of the array substrate according to  claim 19 , wherein the source-drain layer comprises a source contact portion, a drain contact portion, a first connection terminal, and a second connection terminal disposed separated from each other; and the first connection terminal and the second connection terminal are disposed on one side of the drain contact portion away from the source contact portion.