US2025098176A1PendingUtilityA1

Magnetic memory device

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Sep 19, 2023Filed: Mar 18, 2024Published: Mar 20, 2025
Est. expirySep 19, 2043(~17.1 yrs left)· nominal 20-yr term from priority
Inventors:Kilho Lee
H10B 61/00H10N 50/80H10N 50/10
63
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A magnetic memory device may include conductive lines provided in cell region and peripheral region, a first insulating layer provided in the cell region and the peripheral region, and surrounding the conductive lines, a second insulating layer provided on the first insulating layer in the cell region and the peripheral region, and on top surfaces of the conductive lines, and data storage patterns provided on the second insulating layer in the cell region and electrically connected to corresponding conductive lines of the conductive lines. The second insulating layer in the peripheral region may include first portions on the top surfaces of the conductive lines, and second portions disposed between the first portions. Top surfaces of the first portions may be disposed at a level higher than top surfaces of the second portions.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A magnetic memory device, comprising:
 a plurality of conductive lines provided in a cell region and a peripheral region;   a first insulating layer provided in the cell region and the peripheral region, and surrounding the plurality of conductive lines;   a second insulating layer provided on the first insulating layer in the cell region and the peripheral region, and on top surfaces of the plurality of conductive lines; and   a plurality of data storage patterns provided on the second insulating layer in the cell region and electrically connected to corresponding first conductive lines of the plurality of conductive lines,   wherein the second insulating layer in the peripheral region comprises a plurality of first portions on the top surfaces of corresponding second conductive lines of the plurality of conductive lines, and a plurality of second portions disposed between the plurality of first portions, and   top surfaces of the plurality of first portions are disposed at a level higher than top surfaces of the plurality of second portions.   
     
     
         2 . The magnetic memory device of  claim 1 , further comprising a substrate provided in the cell region and the peripheral region,
 wherein the first insulating layer is provided on the substrate,   the cell region and the peripheral region of the substrate extend in a first direction that is parallel to a top surface of the substrate, and   a width of the plurality of first portions in the first direction is greater than or equal to a width of the plurality of conductive lines in the first direction.   
     
     
         3 . The magnetic memory device of  claim 1 , further comprising a plurality of bottom electrode contacts provided between the plurality of data storage patterns and the plurality of conductive lines,
 wherein the plurality of bottom electrode contacts are connected to the plurality of data storage patterns, respectively,   each of the plurality of bottom electrode contacts is connected to a corresponding conductive line of the first conductive lines, and   a height of the plurality of bottom electrode contacts is equal to a vertical thickness of the plurality of first portions.   
     
     
         4 . The magnetic memory device of  claim 3 , further comprising a plurality of first cell conductive lines, which are disposed on the plurality of data storage patterns and are connected to the plurality of data storage patterns. 
     
     
         5 . The magnetic memory device of  claim 1 , wherein the second insulating layer in the peripheral region has a first recess region, which is recessed toward the first insulating layer between the plurality of first portions. 
     
     
         6 . The magnetic memory device of  claim 5 , further comprising a peripheral insulating layer provided on the second insulating layer in the peripheral region,
 wherein the peripheral insulating layer fills the first recess region, and   the peripheral insulating layer has a dielectric constant less than the second insulating layer.   
     
     
         7 . The magnetic memory device of  claim 1 , wherein the plurality of first portions have different crystal structures from the plurality of second portions. 
     
     
         8 . The magnetic memory device of  claim 1 , wherein the second insulating layer comprises a carbon nitride (CN), and
 a fraction of a sp 3  C—N bonding in the plurality of first portions is greater than a fraction of a sp 3  C—N bonding in the plurality of second portions.   
     
     
         9 . The magnetic memory device of  claim 3 , wherein the second insulating layer in the cell region has a second recess region, which is recessed toward the first insulating layer between the plurality of data storage patterns, and
 a lowermost portion of a top surface of the second recess region is located at a level lower than a top surface of the plurality of bottom electrode contacts.   
     
     
         10 . The magnetic memory device of  claim 1 , further comprising a plurality of peripheral conductive lines provided on the first insulating layer in the peripheral region,
 wherein each of the plurality of peripheral conductive lines penetrates the first portion and is connected to a corresponding conductive contact of the second conductive contacts.   
     
     
         11 . A magnetic memory device, comprising:
 a substrate including a cell region and a peripheral region;   a plurality of conductive lines provided in the cell region and the peripheral region of the substrate;   a first insulating layer provided on the substrate in the cell region and the peripheral region, and surrounding the conductive lines;   a second insulating layer disposed on the first insulating layer in the cell region to cover top surfaces of corresponding first conductive lines of the plurality of conductive lines;   a plurality of data storage patterns disposed on the second insulating layer in the cell region and electrically connected to the corresponding first conductive lines;   a plurality of insulating patterns disposed on the first insulating layer in the peripheral region on top surfaces of corresponding second conductive lines of the plurality of conductive lines; and   a peripheral insulating layer disposed on the first insulating layer in the peripheral region and between the plurality of insulating patterns,   wherein the peripheral insulating layer has dielectric constant lower than a dielectric constant of the second insulating layer and a dielectric constant of the plurality of insulating patterns.   
     
     
         12 . The magnetic memory device of  claim 11 , wherein the plurality of insulating patterns and the second insulating layer have different crystal structures from each other. 
     
     
         13 . The magnetic memory device of  claim 12 , wherein the second insulating layer and the plurality of insulating patterns comprise a carbon nitride (CN), and
 a fraction of a sp 3  C—N crystal in the plurality of insulating patterns is greater than a fraction of a sp 3  C—N crystal in the second insulating layer.   
     
     
         14 . The magnetic memory device of  claim 11 , wherein a width of each of the plurality of insulating patterns in a first direction is greater than or equal to a width of each of the plurality of conductive lines in the first direction, and
 the first direction is parallel to a top surface of the substrate.   
     
     
         15 . The magnetic memory device of  claim 11 , further comprising a plurality of bottom electrode contacts disposed between the plurality of data storage patterns and the plurality of conductive lines,
 wherein the plurality of bottom electrode contacts are connected to the plurality of data storage patterns, respectively,   each bottom electrode contact of the plurality of bottom electrode contacts is connected to a corresponding conductive line of the plurality of conductive lines, and   a height of the plurality of bottom electrode contacts is equal to a height of the plurality of insulating patterns.   
     
     
         16 . The magnetic memory device of  claim 11 , wherein the second insulating layer has a recess region, which is disposed between the plurality of data storage patterns and is recessed toward the substrate, and
 a lowermost portion of a top surface of the recess region of the second insulating layer is located at a level lower than top surfaces of the plurality of insulating patterns.   
     
     
         17 . A magnetic memory device, comprising:
 a substrate including a cell region and a peripheral region;   a plurality of conductive lines provided in the cell region and the peripheral region of the substrate;   a first insulating layer provided on the substrate in the cell region and the peripheral region, surrounding the plurality of conductive lines;   a second insulating layer disposed on the first insulating layer in the cell region and the peripheral region to cover top surfaces of the plurality of conductive lines; and   a plurality of data storage patterns disposed on the second insulating layer in the cell region and electrically connected to corresponding conductive lines of the plurality of conductive lines,   wherein the second insulating layer in the peripheral region comprises a first portion covering top surfaces of the plurality of conductive lines in the peripheral region, and   the plurality of first portions have a crystal structure different from a crystal structure of the second insulating layer in the cell region.   
     
     
         18 . The magnetic memory device of  claim 17 , wherein a width of the plurality of first portions in a first direction is greater than or equal to a width of the plurality of conductive lines in the first direction, and
 the first direction is parallel to a top surface of the substrate.   
     
     
         19 . The magnetic memory device of  claim 17 , further comprising a plurality of bottom electrode contacts disposed between the plurality of data storage patterns and the plurality of conductive lines,
 wherein the plurality of bottom electrode contacts are connected to the plurality of data storage patterns, respectively,   each of the plurality of bottom electrode contacts is connected to a corresponding first conductive line of the plurality of conductive lines, and   a height of the plurality of bottom electrode contacts is equal to a vertical thickness of the first portion.   
     
     
         20 . The magnetic memory device of  claim 17 , wherein the second insulating layer in the peripheral region has a recess region, which is disposed between the first portions and is recessed toward the substrate, and
 a lowermost portion of a top surface of the recess region is located at a level lower than top surfaces of the first portions.

Join the waitlist — get patent alerts

Track US2025098176A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.