Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; a second semiconductor layer provided above the first semiconductor layer; a third semiconductor layer interposed between the first and second semiconductor layers; a stacked body provided above the second semiconductor layer, in which a plurality of conductive layers are stacked one by one while being separated from each other; and a pillar including a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body and reaches a predetermined depth of the first semiconductor layer. The channel layer is electrically connected to the third semiconductor layer on a side surface. The pillar has a cross-sectional area as viewed from the stacking direction that is larger at a height position of the first semiconductor layer than at a height position of the third semiconductor layer, and has a stepped portion at a height position of an interface between the first semiconductor layer and the third semiconductor layer.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a first semiconductor layer;   a second semiconductor layer provided above the first semiconductor layer;   a third semiconductor layer interposed between the first and second semiconductor layers;   a stacked body provided above the second semiconductor layer, in which a plurality of conductive layers are stacked one by one while being separated from each other; and   a pillar including a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body and reaches a predetermined depth of the first semiconductor layer, wherein   the channel layer is electrically connected to the third semiconductor layer on a side surface, and   the pillar has a cross-sectional area as viewed from the stacking direction that is larger at a height position of the first semiconductor layer than at a height position of the third semiconductor layer, and has a stepped portion at a height position of an interface between the first semiconductor layer and the third semiconductor layer.   
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein
 the pillar is included in a plurality of pillars, and   the plurality of pillars are provided independently of each other.   
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein
 the pillar is included in a plurality of pillars, and   the plurality of pillars are connected to each other at a height position of the first semiconductor layer.   
     
     
         4 . The semiconductor memory device according to  claim 1 , wherein
 a center point of a cross section of the pillar viewed from the stacking direction does not coincide between the height position of the first semiconductor layer and the height position of the third semiconductor layer.   
     
     
         5 . The semiconductor memory device according to  claim 4 , wherein
 the channel layer extends along an outer shape of the pillar, and has a layer thickness different from a layer thickness of other portions at the stepped portion.   
     
     
         6 . The semiconductor memory device according to  claim 4 , wherein
 the center point at the height position of the first semiconductor layer is shifted in a first direction along the cross section with respect to the center point at the height position of the third semiconductor layer, and   the channel layer at the stepped portion is thicker in a second direction opposite to the first direction than in the first direction.   
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein
 the channel layer discontinuously extends from the third semiconductor layer to the first semiconductor layer in the first direction.   
     
     
         8 . The semiconductor memory device according to  claim 6 , wherein
 the third semiconductor layer contains an impurity of a first conductivity type.   
     
     
         9 . The semiconductor memory device according to  claim 8 , wherein
 the channel layer contains the impurity in a predetermined range including a conducting portion with the third semiconductor layer, and   the impurity in the channel layer reaches a height position of the same conductive layer among the plurality of conductive layers on the first direction side and on the second direction side of the channel layer.   
     
     
         10 . A semiconductor memory device comprising:
 a first semiconductor layer;   a second semiconductor layer provided above the first semiconductor layer;   a third semiconductor layer interposed between the first and second semiconductor layers;   a stacked body provided above the second semiconductor layer, in which a plurality of conductive layers are stacked one by one while being separated from each other; and   a plurality of pillars each including a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body, wherein   each of the channel layers is electrically connected to the third semiconductor layer on a side surface, and   the plurality of pillars are connected to each other at a height position of the first semiconductor layer.   
     
     
         11 . A method of manufacturing a semiconductor memory device, comprising:
 forming a first semiconductor layer;   forming a recess in the first semiconductor layer;   forming a stopper layer in the recess;   forming a first sacrificial layer above the first semiconductor layer on which the stopper layer is formed;   forming a second semiconductor layer above the first sacrificial layer;   forming a stacked body in which a plurality of second sacrificial layers are stacked one by one while being separated from each other above the second semiconductor layer;   forming a memory hole that extends through the stacked body, the second semiconductor layer, and the first sacrificial layer in a stacking direction of the stacked body and reaches the stopper layer; and   forming a channel layer in the memory hole.   
     
     
         12 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising:
 removing the stopper layer from the inside of the recess before forming the channel layer; and   when forming the channel layer, forming the channel layer so as to cover a side wall of the memory hole, a side wall of the recess, and a bottom surface of the recess.   
     
     
         13 . The method of manufacturing a semiconductor memory device according to  claim 12 , further comprising:
 removing the first sacrificial layer to expose the channel layer at a height position of the first sacrificial layer; and   forming a third semiconductor layer in a gap generated by removing the first sacrificial layer to electrically connect to the channel layer.   
     
     
         14 . The method of manufacturing a semiconductor memory device according to  claim 13 , further comprising:
 forming a multilayer insulating layer covering the side wall of the memory hole, the side wall of the recess, and the bottom surface of the recess before forming the channel layer;   after forming the channel layer via the multilayer insulating layer, removing the first sacrificial layer to expose the multilayer insulating layer at the height position of the first sacrificial layer; and   removing the multilayer insulating layer exposed at the height position of the first sacrificial layer to expose the channel layer.   
     
     
         15 . The method of manufacturing a semiconductor memory device according to  claim 13 , further comprising
 when forming the third semiconductor layer, including an impurity of a first conductivity type in the third semiconductor layer.   
     
     
         16 . The method of manufacturing a semiconductor memory device according to  claim 15 , further comprising
 when forming the third semiconductor layer, also including the impurity in the channel layer via the third semiconductor layer.   
     
     
         17 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising:
 when forming the recess, forming a plurality of recesses in the first semiconductor layer; and   when forming the memory hole, forming a plurality of memory holes respectively reaching the plurality of recesses.   
     
     
         18 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising
 when forming the memory hole, forming a plurality of memory holes reaching the stopper layer formed in the recess.   
     
     
         19 . The method of manufacturing a semiconductor memory device according to  claim 11 , further comprising
 when forming the memory hole, making a cross-sectional area of a lower end of the memory hole as viewed from the stacking direction smaller than a cross-sectional area of an upper surface of the recess.   
     
     
         20 . The method of manufacturing a semiconductor memory device according to  claim 19 , further comprising
 when forming the memory hole, allowing positional deviation within a predetermined range between a center point of a cross section of the memory hole and a center point of a cross section of the recess when viewed from the stacking direction.