Vertical power component

Abstract

The present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. The component includes: an active region ( 100 A); and first and second groups of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof. The second semiconductor region has a width at least three times larger than the width of the widest first semiconductor region.

1 . A vertical power component comprising:
 a semiconductor substrate doped with a first conductivity type;   a semiconductor layer doped with the first conductivity type on the semiconductor substrate;   an active region;   first and second groups of first field limiting rings surrounding the active region, each of the first field limiting rings including a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending into a thickness of the semiconductor layer;   a second field limiting ring laterally interposed between the first and second groups of the first field limiting rings, the second field limiting ring including a second semiconductor region doped with the second conductivity type, extending into the thickness of the semiconductor layer; and   a first insulating region on and in mechanical contact with an entire face of the second semiconductor region,   wherein the second semiconductor region has a width at least three times larger than a width of the widest first semiconductor region.   
     
     
         2 . The vertical power component according to  claim 1 , further comprising:
 a second insulating region located in a peripheral region of the vertical power component,   wherein the second field limiting ring is configured to reduce, by at least half, an electric field present in a vicinity of an interface between the first insulating region and the second insulating region.   
     
     
         3 . The vertical power component according to  claim 1 , wherein the second field limiting ring enables to reduce, by at least half, an electric field present in a vicinity of an interface between the first insulating region and a molding resin of a package of the vertical power component. 
     
     
         4 . The vertical power component according to  claim 1 , wherein the first and second groups include identical numbers of the first field limiting rings. 
     
     
         5 . The vertical power component according to  claim 1 , wherein the first field limiting rings and the second field limiting ring are floating guard rings. 
     
     
         6 . The vertical power component according to  claim 1 , further comprising:
 at least one third group of the first field limiting rings; and   at least one third field limiting ring interposed between the second group of the first field limiting rings and the at least one third group of the first field limiting rings.   
     
     
         7 . The vertical power component according to  claim 1 , wherein the semiconductor layer has a doping level that is lower than that of the semiconductor substrate. 
     
     
         8 . The vertical power component according to  claim 1 , further comprising:
 a first conduction electrode formed in the active region, and including a conductive region located on the semiconductor layer; and   a second conduction electrode arranged on a side of a face of the semiconductor substrate opposite the semiconductor layer.   
     
     
         9 . The vertical power component according to  claim 1 , wherein the semiconductor substrate is made of silicon or of silicon carbide. 
     
     
         10 . The vertical power component according to  claim 1 , wherein the first conductivity type is N and the second conductivity type is P. 
     
     
         11 . The vertical power component according to  claim 1 , wherein the vertical power component is a Junction-Barrier Schottky (JBS) diode. 
     
     
         12 . A device comprising:
 a semiconductor substrate having a first conductivity type;   a semiconductor layer on the semiconductor substrate, the semiconductor layer having the first conductivity type; and   a power component on the semiconductor layer, the power component including an active region and a peripheral region surrounding the active region, the peripheral region including:
 a first plurality of first semiconductor regions extending into the semiconductor layer, the first semiconductor regions having a second conductivity type; 
 a second semiconductor region extending into the semiconductor layer, the second semiconductor region having a width that is larger than each of the widths of the first semiconductor regions; and 
 a second plurality of the first semiconductor regions extending into the semiconductor layer, the first plurality of the first semiconductor regions being spaced from the second plurality of the first semiconductor regions by the second semiconductor region. 
   
     
     
         13 . The device of  claim 12 , wherein the width of the second semiconductor region is at least three times larger than each of the widths of the first semiconductor regions. 
     
     
         14 . The device of  claim 12 , further comprising:
 a first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second semiconductor region, and the second plurality of the first semiconductor regions.   
     
     
         15 . The device of  claim 14  wherein the first insulating region physically contacts an entire face of the second semiconductor region. 
     
     
         16 . The device of  claim 14  wherein the active region includes a conductive region on the semiconductor layer, and the first insulating region is on the conductive region. 
     
     
         17 . The device of  claim 16 , further comprising:
 a second insulating region on the first insulating region and the conductive region.   
     
     
         18 . The device of  claim 12  wherein the semiconductor layer is an epitaxial layer. 
     
     
         19 . A device comprising:
 a semiconductor substrate having a first conductivity type;   a semiconductor layer on the semiconductor substrate, the semiconductor layer having the first conductivity type;   an active region in and on the semiconductor layer; and   a peripheral region surrounding the active region, the peripheral region including:
 a first plurality of first semiconductor regions in the semiconductor layer; 
 a second plurality of the first semiconductor regions in the semiconductor layer, the first semiconductor regions having a second conductivity type; 
 a second semiconductor region in the semiconductor layer and between the first plurality of the first semiconductor regions and the second plurality of the first semiconductor regions, the second semiconductor region having a width that is larger than each of the widths of the first semiconductor regions; and 
 a first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second plurality of the first semiconductor regions, and the second semiconductor region. 
   
     
     
         20 . The device of  claim 19  wherein each of the first semiconductor regions and the second semiconductor region has a smaller thickness than the semiconductor layer.