Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device includes a bit line on a peripheral gate structure and extending in a second direction different from a first direction; a shielding structure adjacent to the bit line on the peripheral gate structure and extending in the second direction; a back gate electrode on the bit line and the shielding structure and extending in the first direction; a first word line extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line placed on another side of the back gate electrode, the first and second word lines on the bit line and the shielding structure; and a first activation pattern between the back gate electrode and the first word line and a second activation pattern, the first and second activation patterns on the bit line, wherein the shielding structure includes a low-dielectric material.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a peripheral gate structure on a substrate;   a bit line on the peripheral gate structure, and extending in a second direction different from a first direction;   a shielding structure on the peripheral gate structure, adjacent to the bit line, and extending in the second direction;   a back gate electrode on the bit line and the shielding structure and extending in the first direction;   a first word line on the bit line and the shielding structure, extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line on the bit line and the shielding structure and on another side of the back gate electrode; and   a first activation pattern on the bit line and between the back gate electrode and the first word line and a second activation pattern between the back gate electrode and the second word line,   wherein the shielding structure includes a low-dielectric material.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein:
 a dielectric constant of the low-dielectric material is less than that of silicon oxide (SiO 2 ).   
     
     
         3 . The semiconductor memory device of  claim 2 , wherein:
 the low-dielectric material includes a hydrocarbon compound, carbide, carbon, or a combination thereof.   
     
     
         4 . The semiconductor memory device of  claim 2 , wherein:
 the low-dielectric material includes at least one of carbon doping silicon oxide (SiOC) or porous silicon oxide.   
     
     
         5 . The semiconductor memory device of  claim 1 , wherein:
 the shielding structure includes a shielding pattern, and a shielding insulation layer between the shielding pattern and the bit line.   
     
     
         6 . The semiconductor memory device of  claim 5 , wherein:
 the shielding pattern includes a conductive material, and   the shielding insulation layer includes the low-dielectric material.   
     
     
         7 . The semiconductor memory device of  claim 5 , wherein:
 the shielding pattern includes the low-dielectric material, and   the shielding insulation layer includes an insulating material.   
     
     
         8 . The semiconductor memory device of  claim 1 , wherein:
 the shielding structure includes a body portion below the bit line and extending in the first direction and the second direction, and an extension portion between the bit lines and extending in the second direction.   
     
     
         9 . The semiconductor memory device of  claim 1 , wherein:
 the first activation pattern and the second activation pattern include a monocrystalline semiconductor material.   
     
     
         10 . The semiconductor memory device of  claim 1 , further comprising:
 a bonding insulation layer between the peripheral gate structure and the bit line.   
     
     
         11 . A semiconductor memory device comprising:
 a peripheral gate structure on a substrate;   a bit line on the peripheral gate structure, and extending in a second direction different from a first direction;   a shielding structure adjacent to the bit line on the peripheral gate structure and extending in the second direction;   a back gate electrode on the bit line and the shielding structure and extending in the first direction;   a first word line on the bit line and the shielding structure, extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line on the bit line and the shielding structure and on another side of the back gate electrode; and   a first activation pattern on the bit line between the back gate electrode and the first word line and a second activation pattern placed the back gate electrode and the second word line,   wherein the shielding structure has an air gap.   
     
     
         12 . The semiconductor memory device of  claim 11 , wherein:
 the shielding structure includes a shielding pattern and a shielding insulation layer between the shielding pattern and the bit line.   
     
     
         13 . The semiconductor memory device of  claim 12 , wherein:
 the shielding pattern includes a low-dielectric material, and   the shielding insulation layer has the air gap.   
     
     
         14 . The semiconductor memory device of  claim 12 , wherein:
 the shielding pattern includes a conductive material, and   the shielding insulation layer has the air gap.   
     
     
         15 . The semiconductor memory device of  claim 12 , wherein:
 the shielding pattern includes an insulating material, and   the shielding insulation layer has the air gap.   
     
     
         16 . The semiconductor memory device of  claim 15 , wherein:
 the shielding pattern has a second air gap.   
     
     
         17 . The semiconductor memory device of  claim 15 , wherein:
 the shielding structure has the air gap between the shielding pattern and the shielding insulation layer.   
     
     
         18 . The semiconductor memory device of  claim 12 , wherein:
 one end of the air gap in a third direction different from the first direction and the second direction is in contact with the shielding pattern, and   another end of the air gap in the third direction is surrounded by the shielding insulation layer.   
     
     
         19 . The semiconductor memory device of  claim 11 , wherein:
 the bit line includes a bit line mask pattern, a metal pattern, and a polysilicon pattern sequentially stacked in a third direction different from the first direction and the second direction, and   the air gap extends in the third direction and overlaps the metal pattern in the first direction.   
     
     
         20 . A semiconductor memory device comprising:
 a peripheral gate structure on a substrate;   a bit line on the peripheral gate structure, and extending in a second direction different from a first direction;   a shielding structure adjacent to the bit line on the peripheral gate structure and extending in the second direction;   a back gate electrode on the bit line and the shielding structure and extending in the first direction;   a first word line extending in the first direction and on one side of the back gate electrode in the second direction, and a second word line placed on another side of the back gate electrode, the first and second word lines on the bit line and the shielding structure; and   a first activation pattern between the back gate electrode and the first word line and a second activation pattern between the back gate electrode and the second word line, the first and second activation patterns on the bit line,   wherein the shielding structure includes a shielding pattern, and a shielding insulation layer placed between the shielding pattern and the bit line,   the shielding pattern includes a conductive material, and   the shielding insulation layer includes a low-dielectric material, and/or the shielding insulation layer has an air gap.