Wide Bandgap Trench Gate Semiconductor Device with Buried Gate

Abstract

Wide bandgap trench gate semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap semiconductor structure. The wide bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench in the wide bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a buried gate structure in the gate trench. The buried gate structure includes a gate polysilicon layer and a gate silicide layer.

1 . A semiconductor device, comprising:
 a wide bandgap semiconductor structure, the wide bandgap semiconductor structure comprising a drift region of a first conductivity type and a well region of a second conductivity type;   a gate trench in the wide bandgap semiconductor structure, the gate trench extending through the well region into the drift region; and   a buried gate structure in the gate trench, the buried gate structure comprising a gate polysilicon layer and a gate silicide layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein an upper surface of the gate silicide layer is below an upper surface of the wide bandgap semiconductor structure. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the buried gate structure is covered within the gate trench. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the gate silicide layer comprises Ta y Si x  or W y Si x , wherein x is in a range of about 2.0 to about 3.0. 
     
     
         5 . (canceled) 
     
     
         6 . The semiconductor device of  claim 1 , wherein the gate polysilicon layer has a different width relative to a width of the gate silicide layer. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the gate polysilicon layer is between the gate silicide layer and a bottom surface of the gate trench. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate silicide layer is closer to an upper surface of the wide bandgap semiconductor structure relative to the gate polysilicon layer. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a dielectric layer in the gate trench on the buried gate structure. 
     
     
         10 . The semiconductor device of  claim 9 , further comprising a metallization layer on the wide bandgap semiconductor structure, the metallization layer having a planar surface contacting the wide bandgap semiconductor structure and the dielectric layer, wherein the dielectric layer is arranged to electrically insulate the buried gate structure from the metallization layer. 
     
     
         11 . (canceled) 
     
     
         12 . The semiconductor device of  claim 9 , wherein the dielectric layer has an upper surface that is coplanar with an upper surface of the semiconductor structure. 
     
     
         13 . The semiconductor device of  claim 9 , wherein the dielectric layer is a silicate glass. 
     
     
         14 . The semiconductor device of  claim 1 , further comprising a spacer layer in the gate trench, the spacer layer between at least a portion of the buried gate structure and a sidewall of the gate trench. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the spacer layer comprises silicon dioxide or silicon nitride. 
     
     
         16 . (canceled) 
     
     
         17 . The semiconductor device of  claim 1 , further comprising a gate dielectric layer between the buried gate structure and the drift region, wherein the gate dielectric layer has a thickness between the buried gate structure and a bottom surface of the buried gate structure, the thickness being in a range of about 250 Angstroms to about 2500 Angstroms. 
     
     
         18 . (canceled) 
     
     
         19 . The semiconductor device of  claim 1 , wherein the semiconductor structure comprises a second silicide layer on an upper surface of the wide bandgap semiconductor structure, wherein the second silicide layer is a different material relative to the gate silicide layer, wherein the second silicide layer comprises nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, aluminum-titanium silicide, nickel-titanium-aluminum silicide or titanium-tungsten silicide. 
     
     
         20 . (canceled) 
     
     
         21 . (canceled) 
     
     
         22 . The semiconductor device of  claim 1 , wherein the wide bandgap semiconductor structure further comprises a shield region beneath the gate trench, the shield region having the second conductivity type. 
     
     
         23 . The semiconductor device of  claim 1 , wherein the wide bandgap semiconductor structure comprises silicon carbide. 
     
     
         24 . The semiconductor device of  claim 1 , wherein the semiconductor device is a MOSFET or an insulated gate bipolar transistor (IGBT). 
     
     
         25 . (canceled) 
     
     
         26 . A semiconductor device, comprising:
 a wide bandgap semiconductor structure, the wide bandgap semiconductor structure comprising a drift region of a first conductivity type and a well region of a second conductivity type;   a gate trench in the wide bandgap semiconductor structure, the gate trench extending through the well region into the drift region;   a gate structure in the gate trench;   a dielectric layer in the gate trench and on the gate structure;   a spacer layer in the gate trench and between the dielectric layer and a sidewall of the gate trench; and   a gate dielectric layer in the gate trench between the gate structure and the drift region.   
     
     
         27 .- 48 . (canceled) 
     
     
         49 . A method of fabricating a semiconductor device, the method comprising:
 forming a gate trench in a wide bandgap semiconductor structure;   forming a buried gate structure in the gate trench, the buried gate structure comprising a gate polysilicon layer and a gate silicide layer; and   forming a dielectric layer in the gate trench and on the buried gate structure.   
     
     
         50 .- 60 . (canceled)