Sensor circuit

Abstract

The present disclosure relates to a sensor circuit including an analog chopper circuit configured to shift an analog input signal from an original frequency to a chopping frequency to generate a chopped analog signal, a ΣΔ-modulator coupled to an output of the analog chopper circuit and configured to digitize the chopped analog signal at a sampling frequency to generate a chopped digital signal, and a digital chopper circuit coupled to an output of the ΣΔ-modulator and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the original frequency.

1 . A sensor circuit, comprising:
 an analog chopper circuit configured to shift an analog input signal from an original frequency to a chopping frequency to generate a chopped analog signal;   a sigma-delta (CA)-modulator coupled to an output of the analog chopper circuit and configured to digitize the chopped analog signal at a sampling frequency to generate a chopped digital signal; and   a digital chopper circuit coupled to an output of the ΣΔ-modulator and configured to demodulate the chopped digital signal to generate a demodulated chopped digital signal having a signal component at the original frequency.   
     
     
         2 . The sensor circuit of  claim 1 , wherein the ΣΔ-modulator is configured without a chopper circuit. 
     
     
         3 . The sensor circuit of  claim 1 , wherein a ratio between the sampling frequency of the ΣΔ-modulator and the chopping frequency is larger than 100. 
     
     
         4 . The sensor circuit of  claim 1 , wherein the ΣΔ-modulator comprises an analog-to-digital converter (ADC) ADC and an analog loop filter coupled between the output of the analog chopper circuit and the ADC. 
     
     
         5 . The sensor circuit of  claim 4 , wherein the analog loop filter is implemented as continuous time loop filter. 
     
     
         6 . The sensor circuit of  claim 1 , wherein the CA-modulator comprises a first multi-bit analog-to-digital converter (ADC) configured to convert the chopped analog signal from analog to digital to generate the chopped digital signal. 
     
     
         7 . The sensor circuit of  claim 6 , wherein the first multi-bit ADC has a bit width equal to or larger than two bits. 
     
     
         8 . The sensor circuit of  claim 6 , wherein the ΣΔ-modulator comprises a feedback path that extends from the output of the ΣΔ-modulator to an input of the ΣΔ-modulator, the feedback path comprising a second multi-bit DAC configured to convert the chopped digital signal back to analog. 
     
     
         9 . The sensor circuit of  claim 8 , wherein the second multi-bit DAC has a bit width equal to or larger than two bits. 
     
     
         10 . The sensor circuit of  claim 1 , wherein the ΣΔ-modulator comprises a single-bit analog-to-digital converter (ADC) configured to convert the chopped analog signal from analog to digital to generate the chopped digital signal. 
     
     
         11 . The sensor circuit of  claim 10 , wherein the ΣΔ-modulator comprises a feedback path that extends from the output of the ΣΔ-modulator to an input of the ΣΔ-modulator, the feedback path comprising a single-bit digital-to-analog converter (DAC) configured to convert the chopped digital signal back to analog. 
     
     
         12 . The sensor circuit of  claim 1 , further comprising:
 a digital filter coupled to an output of the digital chopper circuit and configured to reject at least the chopping frequency.   
     
     
         13 . The sensor circuit of  claim 12 , wherein the digital filter comprises a notch filter having a notch at least at the chopping frequency. 
     
     
         14 . The sensor circuit of  claim 12 , wherein the digital filter comprises a lowpass filter configured to allow the signal component at the original frequency to pass through while attenuating signal components at the chopping frequency or higher. 
     
     
         15 . The sensor circuit of  claim 12 , wherein the digital filter comprises a combination of a lowpass filter and a notch filter. 
     
     
         16 . The sensor circuit of  claim 1 , further comprising:
 a digital filter coupled between the ΣΔ-modulator and the digital chopper circuit and configured to reject harmonics of the chopping frequency.   
     
     
         17 . The sensor circuit of  claim 16 ,
 wherein the digital filter is configured to cause a filter delay,   wherein the sensor circuit further comprises a delay element coupled between a chopping clock signal and the digital chopper circuit, and   wherein the delay element is configured to cause a delay of the chopping clock signal corresponding to the filter delay.   
     
     
         18 . The sensor circuit of  claim 1 , further comprising:
 an amplifier coupled between the analog chopper circuit and the ΣΔ-modulator and configured to amplify the chopped analog signal.   
     
     
         19 . The sensor circuit of  claim 1 , wherein the digital chopper circuit is configured to multiply the chopped digital signal with a digital sinusoidal signal having the chopping frequency.