Linear regulator, semiconductor device, and switching power supply

Abstract

A linear regulator includes: a first transistor of an N-channel type configured to be connected between an application terminal for an input terminal and an application terminal for a stabilized voltage; a second transistor of an N-channel type configure to, by forming a current mirror type output stage with the first transistor, generate an output current flowing in the first transistor by mirroring a bias current flowing in the second transistor itself; a feedback controller circuit configured to control the bias current according to the difference between a feedback voltage corresponding to the stabilized voltage and a predetermined reference voltage; and a load configured to draw a first leakage current from a control terminal common to the first and second transistors.

1 . A linear regulator comprising:
 a first transistor of an N-channel type configured to be connected between an application terminal for an input terminal and an application terminal for a stabilized voltage;   a second transistor of an N-channel type configured to, by forming a current mirror type output stage with the first transistor, generate an output current flowing in the first transistor by mirroring a bias current flowing in the second transistor itself;   a feedback controller configured to control the bias current according to a difference between a feedback voltage corresponding to the stabilized voltage and a predetermined reference voltage; and   a load configured to draw a first leakage current from a control terminal common to the first and second transistors.   
     
     
         2 . The linear regulator according to  claim 1 , wherein the load includes a third transistor of an N-channel type configured to have same leakage current characteristics as the first transistor. 
     
     
         3 . The linear regulator according to  claim 1 , further comprising a bias current adjuster configured to increase the bias current by at least a same amount as the first leakage current when the first transistor is turned on. 
     
     
         4 . The linear regulator according to  claim 3 , wherein the bias current adjuster includes a fourth transistor of an N-channel type configured to have same leakage current characteristics as the load. 
     
     
         5 . The linear regulator according to  claim 1 , wherein the feedback controller includes:
 a first bias current generation circuit configured to generate a predetermined first bias current;   a second bias current generation circuit configured to generate a second bias current corresponding to the difference between the feedback voltage and the reference voltage; and   a current mirror configured to generate the bias current by mirroring a differential current obtained by subtracting the second bias current from the first bias current.   
     
     
         6 . The linear regulator according to  claim 4 , wherein the feedback controller includes:
 a first bias current generation circuit configured to generate a predetermined first bias current;   a second bias current generation circuit configured to generate a second bias current corresponding to the difference between the feedback voltage and the reference voltage;   a current mirror configured to generate the bias current by mirroring a differential current obtained by subtracting the second bias current from a sum current of a second leakage current flowing in the fourth transistor or a mirror current thereof and the first bias current.   
     
     
         7 . The linear regulator according to  claim 1 , further comprising a sink current generation circuit configured to draw a predetermined sink current from the application terminal for the stabilized voltage. 
     
     
         8 . The linear regulator according to  claim 1 , wherein the output stage has a mirror ratio of 10 or more. 
     
     
         9 . A semiconductor device comprising the linear regulator according to  claim 1 . 
     
     
         10 . A switching power supply comprising the semiconductor device according to  claim 9 , wherein the switching power supply drives a switching output stage to generate a desired output voltage from the input voltage.