Compact efuse structure

Abstract

The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.

What is claimed is: 
     
         1 . An electronic fuse device, comprising:
 a first bit cell comprising a first plurality of active regions extending along a first direction; and   a second bit cell comprising a second plurality of active regions extending along the first direction,   wherein each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction,   wherein the first bit cell and the second bit cell are spaced apart along the first direction by a space,   wherein the space is free of a well tap cell.   
     
     
         2 . The electronic fuse device of  claim 1 , wherein the first plurality of active regions are discontinuous with the second plurality of active regions. 
     
     
         3 . The electronic fuse device of  claim 1 , further comprising:
 at least one isolation gate structure disposed between the first bit cell and the second bit cell.   
     
     
         4 . The electronic fuse device of  claim 3 ,
 wherein the at least one isolation gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer,   wherein the gate electrode comprises metal.   
     
     
         5 . The electronic fuse device of  claim 1 , further comprising:
 at least one grounded gate structure disposed between the first bit cell and the second bit cell,   wherein the at least one grounded gate structure is electrically coupled to a circuit ground.   
     
     
         6 . The electronic fuse device of  claim 1 , further comprising:
 a backside interconnect structure below the first bit cell and the second bit cell; and   a frontside interconnect structure over the first bit cell and the second bit cell.   
     
     
         7 . The electronic fuse device of  claim 6 , further comprising:
 a plurality of dummy active regions extending along the first direction and interleave the plurality of active region,   a plurality of source/drain contacts disposed over the plurality of dummy active regions,   wherein the plurality of source/drain contacts are not electrically coupled to the frontside interconnect structure or the backside interconnect structure.   
     
     
         8 . The electronic fuse device of  claim 6 ,
 wherein the frontside interconnect structure comprises a fuse link,   wherein the fuse link comprises two end portions,   wherein each of the end portions is disposed between two fuse wings.   
     
     
         9 . An electronic fuse device, comprising:
 a first bit cell comprising a first n-type transistor and a first p-type transistor; and   a second bit cell comprising a second n-type transistor and a second p-type transistor,   wherein the first n-type transistor is disposed over a first p-type well,   wherein the first p-type transistor is disposed over a first n-type well,   wherein the first p-type well is insulated from the first n-type well,   wherein the second n-type transistor is disposed over a second p-type well,   wherein the second p-type transistor is disposed over a second n-type well,   wherein the second p-type well is insulated from the second n-type well.   
     
     
         10 . The electronic fuse device of  claim 9 , wherein the first n-type transistor comprises:
 a source feature and a drain feature;   a plurality of channel members extending between the source feature and the drain feature; and   a gate structure wrapping around each of the plurality of channel members.   
     
     
         11 . The electronic fuse device of  claim 10 , further comprising:
 a backside interconnect structure below the first bit cell and the second bit cell;   a frontside interconnect structure over the first bit cell and the second bit cell; and   a backside contact via extending between a bottom surface of the source feature and the backside interconnect structure.   
     
     
         12 . The electronic fuse device of  claim 9 ,
 wherein the first bit cell and the second bit cell are spaced apart by a space,   wherein the space is free of a well tap cell.   
     
     
         13 . The electronic fuse device of  claim 9 , further comprising:
 at least one isolation gate structure disposed between the first bit cell and the second bit cell.   
     
     
         14 . The electronic fuse device of  claim 9 , wherein the at least one isolation gate structure comprises a gate dielectric layer and a gate electrode. 
     
     
         15 . The electronic fuse device of  claim 9 , further comprising:
 at least one grounded gate structure disposed between the first bit cell and the second bit cell,   wherein the at least one grounded gate structure is electrically coupled to a circuit ground.   
     
     
         16 . The electronic fuse device of  claim 9 , further comprising:
 a sense amplifier cell; and   a power switch cell.   
     
     
         17 . An electronic fuse device, comprising:
 a first bit cell comprising a first complementary metal oxide semiconductor (CMOS) device; and   a second bit cell comprising a second CMOS device,   wherein the first CMOS device comprises:
 a first n-type transistor over a first p-type well, 
 a first p-type transistor over a first n-type well, 
   wherein the first p-type well is insulated from the first n-type well by an isolation structure,   wherein the first bit cell and the second bit cell are spaced apart by a space,   wherein the space is free of a well tap cell.   
     
     
         18 . The electronic fuse device of  claim 17 , wherein the first n-type transistor comprises:
 a source feature and a drain feature;   a plurality of channel members extending between the source feature and the drain feature; and   a gate structure wrapping around each of the plurality of channel members.   
     
     
         19 . The electronic fuse device of  claim 18 , further comprising:
 a backside interconnect structure below the first bit cell and the second bit cell;   a frontside interconnect structure over the first bit cell and the second bit cell; and   a backside contact via extending between a bottom surface of the source feature and the backside interconnect structure.   
     
     
         20 . The electronic fuse device of  claim 17 , wherein each of the first bit cell and the second bit cell comprises a rectangular shape.