Semiconductor device

Abstract

The performance of a semiconductor device can be improved. A plurality of protruding electrodes of a semiconductor chip includes: a plurality of first protruding electrodes arranged at positions overlapping a first region of an insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the insulating layer. The plurality of first protruding electrodes is arranged at a first pitch, the plurality of second protruding electrodes is arranged at a second pitch, and the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a wiring substrate;   a semiconductor chip mounted on the wiring substrate via a plurality of protruding electrodes; and   a first insulating material arranged between the semiconductor chip and the wiring substrate, and sealing the plurality of protruding electrodes,   wherein the semiconductor chip includes:
 a semiconductor substrate having a first surface; 
 a first wiring layer formed on the first surface; 
 a second insulating layer arranged so as to cover the first wiring layer, the second insulating layer having a second surface facing the first surface of the semiconductor substrate and a third surface opposite the second surface; and 
 the plurality of protruding electrodes electrically connected with the first wiring layer, 
   wherein, in a plan view, the third surface of the second insulating layer includes:
 a first side extending in a first direction; 
 a second side opposite the first side; 
 a first region located between the first side and the second side; 
 a second region located between the first side and the first region, and located next to the first region; and 
 a third region located between the first side and the second region, and located next to the second region, 
   wherein, in plan view, the plurality of protruding electrodes includes:
 a plurality of first protruding electrodes arranged at positions overlapping the first region; 
 a plurality of second protruding electrodes arranged at positions overlapping the second region; and 
 a plurality of third protruding electrodes arranged at positions overlapping the third region, 
   wherein each of the plurality of third protruding electrodes is electrically connected with a first circuit of the semiconductor chip,   wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with a circuit different from the first circuit,   wherein the plurality of first protruding electrodes is arranged at a first pitch,   wherein the plurality of second protruding electrodes is arranged at a second pitch,   wherein the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch, and   wherein a component in a second direction, which is perpendicular to the first direction, of the second pitch is larger than a component in the second direction of the first pitch.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the plurality of third protruding electrodes of the plurality of protruding electrodes includes a protruding electrode arranged at a position closest to the first side. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the first circuit is an input/output circuit for an electrical signal. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the plurality of second protruding electrodes is arranged in three or more rows in the second direction. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is arranged in a staggered manner. 
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein a minimum pitch between one of the plurality of first protruding electrodes and one, which is located next to the one of the plurality of first protruding electrodes, of the plurality of second protruding electrodes is equal to or greater than the first pitch, and   wherein a minimum pitch between one of the plurality of third protruding electrodes and one, which is located next to the one of the plurality of third protruding electrodes, of the plurality of second protruding electrodes is equal to or greater than the first pitch.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein a maximum pitch between one of the plurality of first protruding electrodes and one, which is located next to the one of the plurality of first protruding electrodes, of the plurality of second protruding electrodes is equal to or less than the second pitch. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein a maximum pitch between one of the plurality of third protruding electrodes and one, which is located next to the one of the plurality of third protruding electrodes, of the plurality of second protruding electrodes is equal to or less than the second pitch. 
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein, in plan view, the third surface of the second insulating layer further includes:
 a third side extending in the second direction; and 
 a fourth region located between the third side and the first region, 
   wherein, in plan view, the plurality of protruding electrodes includes a plurality of fourth protruding electrodes arranged at positions overlapping the fourth region,   wherein each of the plurality of fourth protruding electrodes is electrically connected with a second circuit of the semiconductor chip,   wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with the circuit different from the second circuit, and   wherein the plurality of fourth protruding electrodes is arranged at the first pitch.   
     
     
         10 . The semiconductor device according to  claim 9 , wherein the component in the second direction of the first pitch is longer than a component in the first direction of the first pitch. 
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein each of the plurality of first protruding electrodes is connected with either a power-supply potential supply path that supplies a power-supply potential to the circuit, or a reference potential supply path that supplies a reference potential to the circuit, and   wherein the wiring substrate includes a second wiring layer where a plurality of terminals connected to any of the plurality of first protruding electrodes, the plurality of second protruding electrodes and the plurality of third protruding electrodes is arranged,   wherein the plurality of terminals includes:
 a plurality of power-supply potential terminals electrically connected to the power-supply potential supply path; and 
 a plurality of reference potential terminals electrically connected to the reference potential supply path, and 
   wherein the second wiring layer includes:
 a power-supply potential wiring connected to each of the plurality of power-supply potential terminals arranged in the first direction, and extending in the first direction; and 
 a reference potential wiring connected to each of the plurality of reference potential terminals arranged in the first direction, and extending in the first direction. 
   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein an outer edge of each of the plurality of power-supply potential terminals forms an arc shape, and   wherein a width of the power-supply potential wiring in the second direction is equal to or greater than a radius of each of the plurality of power-supply potential terminals.   
     
     
         13 . The semiconductor device according to  claim 11 ,
 wherein an outer edge of each of the plurality of reference potential terminals forms an arc shape, and   wherein a width of the reference potential wiring in the second direction is equal to or greater than a radius of each of the plurality of reference potential terminals.   
     
     
         14 . A semiconductor device comprising:
 a wiring substrate;   a semiconductor chip mounted on the wiring substrate via a plurality of protruding electrodes; and   a first insulating material arranged between the semiconductor chip and the wiring substrate, and sealing the plurality of protruding electrodes,   wherein the semiconductor chip includes:
 a semiconductor substrate having a first surface; 
 a first wiring layer formed on the first surface; 
 a second insulating layer arranged so as to cover the first wiring layer, the second insulating layer having a second surface facing the first surface of the semiconductor substrate and a third surface opposite the second surface; and 
 the plurality of protruding electrodes electrically connected with the first wiring layer, 
   wherein, in a plan view, the third surface of the second insulating layer includes:
 a first side extending in a first direction; 
 a second side opposite the first side; 
 a first region located between the first side and the second side; 
 a second region located between the first side and the first region; and 
 a third region located between the first side and the second region, 
   wherein, in plan view, the plurality of protruding electrodes includes:
 a plurality of first protruding electrodes arranged at positions overlapping the first region; 
 a plurality of second protruding electrodes arranged at positions overlapping the second region; and 
 a plurality of third protruding electrodes arranged at positions overlapping the third region, 
   wherein each of the plurality of third protruding electrodes is electrically connected with a first circuit of the semiconductor chip,   wherein each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with a circuit different from the first circuit,   wherein the plurality of first protruding electrodes is arranged at a first pitch,   wherein the plurality of second protruding electrodes is arranged at a second pitch,   wherein the plurality of third protruding electrodes is arranged at a third pitch different from each of the first pitch and the second pitch, and   
       wherein a component in a second direction, which is perpendicular to the first direction, of the second pitch is smaller than a component in the second direction of the first pitch.