Managing and maintaining multiple debug contexts in a debug execution mode for real-time processors

Abstract

A method includes executing, by a processor, a first code section having a first priority; encountering, by the processor, during the executing of the first code section, a breakpoint; receiving, by the processor, while at the breakpoint, an interrupt associated with a second code section, the interrupt having a second priority that is higher than the first priority; servicing, by the processor, the interrupt including executing the second code section; receiving a debug access request associated with the breakpoint during the servicing of the interrupt; blocking servicing of the debug access request until servicing of the interrupt is completed; and servicing, by the processor, the debug access request after completing service of the interrupt.

What is claimed is: 
     
         1 . A method comprising:
 executing, by a processor, a first code section having a first priority;   encountering, by the processor, during the executing of the first code section, a breakpoint;   receiving, by the processor, while at the breakpoint, an interrupt associated with a second code section, the interrupt having a second priority that is higher than the first priority;   servicing, by the processor, the interrupt including executing the second code section;   receiving a debug access request associated with the breakpoint during the servicing of the interrupt;   blocking servicing of the debug access request until servicing of the interrupt is completed; and   servicing, by the processor, the debug access request after completing service of the interrupt.   
     
     
         2 . The method of  claim 1 , wherein the debug access request is a first debug access request, the method further comprising:
 receiving a second debug access request associated with the breakpoint during the servicing of the interrupt; and   servicing the debug access request prior to completing service of the interrupt.   
     
     
         3 . The method of  claim 1 , further comprising, based on the interrupt, storing a context associated with breakpoint. 
     
     
         4 . The method of  claim 3 , wherein the context includes at least one of a flag value, a register value, a control signal value, and a memory content. 
     
     
         5 . The method of  claim 4 , further comprising, after completing service of the interrupt, restoring the context. 
     
     
         6 . The method of  claim 1 , wherein the breakpoint is a first breakpoint, the method further comprising:
 encountering a second breakpoint during the servicing of the interrupt; and   based on the second breakpoint, suspending the servicing of the interrupt.   
     
     
         7 . The method of  claim 1 , further comprising:
 suspending, by the processor, the executing of the first code section in response to encountering the breakpoint; and   returning, by the processor, to servicing the breakpoint after completing service of the interrupt.   
     
     
         8 . The method of  claim 1 , wherein the breakpoint is triggered by preprogrammed software or preconfigured hardware. 
     
     
         9 . The method of  claim 6 , wherein the second breakpoint is triggered by a user command. 
     
     
         10 . A computing device comprising:
 a processor configured to service an interrupt associated with a second code section while at a breakpoint encountered during execution of a first code section, in which the interrupt is of higher priority than the breakpoint; and   a debug controller coupled to the processor, wherein the debug controller is configured to issue a debug access request while the processor is at the breakpoint in the first code section;   wherein the processor is further configured to:
 block the debug access request while the interrupt is being serviced; and 
 service the debug access request after the interrupt is serviced. 
   
     
     
         11 . The computing device of  claim 10 , wherein the debug controller is configured to, based on the interrupt, cause the processor to store a context associated with the breakpoint. 
     
     
         12 . The computing device of  claim 11 , wherein the context includes at least one of a flag value, a register value, a control signal value, and a memory content. 
     
     
         13 . The computing device of  claim 12 , wherein the debug controller is configured to, based on completing service of the interrupt, cause the processor to restore the context. 
     
     
         14 . The computing device of  claim 10 , wherein:
 the breakpoint is a first breakpoint;   the processor encounters a second breakpoint while servicing the interrupt; and   the debug controller is configured to cause the processor to suspend servicing of the interrupt based on the second breakpoint.   
     
     
         15 . The computing device of  claim 14 , wherein the second breakpoint has a higher priority than the interrupt. 
     
     
         16 . The computing device of  claim 10 , wherein the debug controller is configured to cause the processor to suspend executing the first code section based on the breakpoint, and cause the processor to return to servicing the breakpoint after completing service of the interrupt. 
     
     
         17 . The computing device of  claim 10 , wherein the debug controller includes a debug monitor. 
     
     
         18 . The computing device of  claim 10 , wherein the debug controller has an input/output terminal configured to interface with a debug host. 
     
     
         19 . The computing device of  claim 10 , further comprising:
 a set of processors that includes the processor; and   a set of debug controllers that includes the debug controller, a respective one of the debug controllers associated with a respective one of the processors.