Method for interfacing a first data reading/ writing unit with a second data reading/writing unit and interface modules thereof

Abstract

The present invention relates to a method for interfacing a first data reading unit ( 245 ) with a second data reading unit ( 260 a ) operatively connected to a data reading interface module ( 310 ), said method comprising:—a data reading request phase, in which a data reading request signal (R-Req) is received by the data reading interface module ( 310 ), the data reading request signal (R-Req) being asserted: —a reading status signalling phase, in which a data reading status signal (R-Stat) is received by the data reading interface module ( 310 ), the data reading status signal (R-Stat) being asserted in the absence of data (Q) in the second data reading unit ( 260 a ); —a reading status verification phase, in which the data reading interface module ( 310 ) verifies if the data reading status signal (R-Stat) is asserted: —if so, the data reading request signal (R-Req) will be unasserted and sent to the second data reading unit ( 260 a ) by the data reading interface module ( 310 ), and a data reading waiting signal (R-Wait) will be asserted and sent to the first data reading unit ( 245 ) by the data reading interface module ( 310 ), —otherwise the data reading interface module ( 310 ) will send the data reading request signal (R-Req) to the second data reading unit ( 260 a ), and the data reading interface module ( 310 ) will receive the data (Q) from the second data reading unit ( 260 a ) and send said data (Q) to the first data reading unit ( 245 ).

1 . Method for interfacing a first data reading unit ( 245 ) with a second data reading unit ( 260   a ) operatively connected to a data reading interface module ( 310 ), said method comprising:
 a data reading request phase, in which a data reading request signal (R-Req) is received by said data reading interface module ( 310 ), said data reading request signal (R-Req) being asserted and sent by said first data reading unit ( 245 );   a reading status signalling phase, in which a data reading status signal (R-Stat) is received by said data reading interface module ( 310 ), wherein the data reading status signal (R-Stat) is sent by said second data reading unit ( 260   a ), said data reading status signal (R-Stat) being asserted in the absence of data (Q) in said second data reading unit ( 260   a );   a reading status verification phase, in which said data reading interface module ( 310 ) verifies if said data reading status signal (R-Stat) is asserted, in which case said data reading interface module ( 310 ) will execute a data reading waiting phase, otherwise it will execute a data reading phase, wherein:   in said data reading waiting phase, the data reading request signal (R-Req) is unasserted and sent to said second data reading unit ( 260   a ) by said data reading interface module ( 310 ), and a data reading waiting signal (R-Wait) is asserted and sent to said first data reading unit ( 245 ) by said data reading interface module ( 310 );   in said data reading phase, said data reading interface module ( 310 ) sends said data reading request signal (R-Req) to said second data reading unit ( 260   a ), and wherein said data reading interface module ( 310 ) receives the data (Q) from said second data reading unit ( 260   a ) and sends said data (Q) to said first data reading unit ( 245 ).   
     
     
         2 . Method according to  claim 1 , wherein said first data reading unit ( 245 ) comprises a first data reading port ( 246 ) that sends said data reading request signal (R-Req) and receives said data reading waiting signal (R-Wait) and/or receives said data (Q),
 and wherein said second data reading unit ( 260   a ) comprises a second data reading port ( 261 ) that receives said data reading request signal (R-Req) and sends said data reading status signal (R-Stat) and/or sends said data (Q),   and wherein said data reading interface module ( 310 ) comprises a third data reading port ( 311 ) that receives said data reading request signal (R-Req) and sends said data reading waiting signal (R-Wait) and/or sends said data (Q), and wherein said data reading interface module ( 310 ) comprises a fourth data reading port ( 312 ) that sends said data reading request signal (R-Req) and receives said reading status signal (R-Stat) and/or receives said data (Q).   
     
     
         3 . Method according to  claim 2 , wherein said first data reading port ( 246 ) and said fourth data reading port ( 312 ) are of the master type, and wherein said second data reading port ( 261 ) and said third data reading port ( 311 ) are of the slave type. 
     
     
         4 . Method according to  claim 1 , wherein a second data reading and writing unit ( 260 ) comprises said second reading unit ( 260   a ), said second data reading and writing unit ( 260 ) comprising a FIFO memory module, and wherein said data reading status signal (R-Stat) comprises an empty FIFO memory signal. 
     
     
         5 . Method according to  claim 1 , wherein said first data reading unit ( 245 ) comprises a DMA module, and wherein said data reading waiting signal (R-Wait) comprises a waitrequest signal. 
     
     
         6 . Method for interfacing a first data writing unit ( 255 ) with a second data writing unit ( 260   b ) operatively connected to a data writing interface module ( 320 ), said method comprising:
 a data writing request phase, in which a data writing request signal (W-Req) is received by said data writing interface module ( 320 ), said data writing request signal (W-Req) being asserted and sent by said first data writing unit ( 255 );   a writing status signalling phase, in which a data writing status signal (W-Stat) is received by said data writing interface module ( 320 ), wherein the data writing status signal (W-Stat) is sent by said second data writing unit ( 260   b ), said data writing status signal (W-Stat) being unasserted in the absence of data (Q) in said second data writing unit ( 260   b );   a writing status verification phase, in which said data writing interface module ( 320 ) verifies if said data writing status signal (W-Stat) is asserted, in which case said data writing interface module ( 320 ) will execute a data writing waiting phase, otherwise it will execute a data writing phase, wherein:   in said data writing waiting phase, the data writing request signal (W-Req) is unasserted and sent to said second data writing unit ( 260   b ) by said data writing interface module ( 320 ), and a data writing waiting signal (W-Wait) is asserted and sent to said first data writing unit ( 255 ) by said data writing interface module ( 320 );   in said data writing phase, said data writing interface module ( 320 ) sends said data writing request signal (W-Req) to said second data writing unit ( 260   b ), and wherein said data writing interface module ( 320 ) receives the data (Q) from said first data writing unit ( 255 ) and sends said data (Q) to said second data writing unit ( 260   b ).   
     
     
         7 . Method according to  claim 6 , wherein said first data writing unit ( 255 ) comprises a first data writing port ( 256 ) that sends said data writing request signal (W-Req) and receives said data writing waiting signal (W-Wait) and/or sends said data (Q),
 and wherein said second data writing unit ( 260   b ) comprises a second data writing port ( 262 ) that receives said data writing request signal (W-Req) and sends said writing status signal (W-Stat) and/or receives said data (Q),   and wherein said data writing interface module ( 320 ) comprises a third data writing port ( 321 ) that receives said data writing request signal (W-Req) and sends said data writing waiting signal (W-Wait) and/or receives said data (Q),   and wherein said data writing interface module ( 320 ) comprises a fourth data writing port ( 322 ) that sends said data writing request signal (W-Req) and receives said data writing status signal (W-Stat) and/or sends said data (Q).   
     
     
         8 . Method according to  claim 7 , wherein said first data writing port ( 256 ) and said fourth data writing port ( 322 ) are of the master type, and wherein said second data writing port ( 262 ) and said third data writing port ( 321 ) are of the slave type. 
     
     
         9 . Method according to  claim 6 , wherein a second data reading and writing unit ( 260 ) comprises said second data writing unit ( 260   b ), said second data reading and writing unit ( 260 ) comprising a FIFO memory module, and wherein said data writing status signal (W-Stat) comprises a full FIFO memory signal. 
     
     
         10 . Method according to  claim 6 , wherein said first data writing unit ( 255 ) comprises a DMA module, and wherein said data writing waiting signal (W-Wait) comprises a waitrequest signal. 
     
     
         11 . Computer program product comprising portions of software code, which can be loaded into an FPGA unit ( 240 ), adapted to implement a data reading interface module ( 310 ) in accordance with the method according to  claim 1 . 
     
     
         12 . System (I  00 ) comprising first processing means (I  10 ), I/0 interface means ( 120 ), memory means ( 130 ) and second processing means ( 200 ) comprising an FPGA unit ( 240 ) adapted to implement a data reading interface module ( 310 ) in accordance with the method according to  claim 1 . 
     
     
         13 . Computer program product comprising portions of software code, which can be loaded into an FPGA unit ( 240 ), adapted to implement a data writing interface module ( 320 ) in accordance with the method according to  claim 6 . 
     
     
         14 . System ( 100 ) comprising first processing means ( 110 ), I/O interface means ( 120 ), memory means ( 130 ) and second processing means ( 200 ) comprising an FPGA unit ( 240 ) adapted to implement a data writing interface module ( 320 ) in accordance with the method according to  claim 6 .