Image sensing circuit and comparator thereof

Abstract

A comparator includes an input stage, a gain stage, an output stage and a clamp circuit. The input stage receives an input signal and a ramp signal and generates a first output signal. The gain stage, coupled to the input stage, receives the first output signal and generates a second output signal. The output stage, coupled to the gain stage, receives the second output signal and generates a third output signal. The clamp circuit, coupled to the gain stage and the output stage.

What is claimed is: 
     
         1 . A comparator, comprising:
 an input stage to receive an input signal and a ramp signal and generate a first output signal;   a gain stage, coupled to the input stage, to receive the first output signal and generate a second output signal;   an output stage, coupled to the gain stage, to receive the second output signal and generate a third output signal; and   a clamp circuit, coupled to the gain stage and the output stage.   
     
     
         2 . The comparator of  claim 1 , wherein the gain stage comprises a high-side transistor and a low-side transistor, and the clamp circuit comprises:
 a first clamp transistor, coupled between the high-side transistor and a power supply terminal of the comparator.   
     
     
         3 . The comparator of  claim 2 , wherein a drain terminal of the first clamp transistor is coupled to the high-side transistor, a source terminal of the first clamp transistor is coupled to the power supply terminal, and a gate terminal of the first clamp transistor is coupled to an output terminal of the gain stage. 
     
     
         4 . The comparator of  claim 2 , wherein the first clamp transistor is a P-type metal oxide semiconductor (PMOS) transistor. 
     
     
         5 . The comparator of  claim 2 , wherein the clamp circuit further comprises a first enable switch, coupled between the first clamp transistor and the power supply terminal. 
     
     
         6 . The comparator of  claim 2 , wherein the first clamp transistor clamps the second output signal to have an upper limit lower than a power supply voltage of the comparator. 
     
     
         7 . The comparator of  claim 1 , wherein the clamp circuit comprises:
 a second clamp transistor, coupled between the gain stage and the output stage.   
     
     
         8 . The comparator of  claim 7 , wherein a first terminal of the second clamp transistor is coupled to an output terminal of the gain stage, a second terminal of the second clamp transistor is coupled to a power supply terminal of the comparator, and a gate terminal of the second clamp transistor is coupled to the output stage. 
     
     
         9 . The comparator of  claim 7 , wherein the second clamp transistor is a PMOS transistor. 
     
     
         10 . The comparator of  claim 7 , wherein the second clamp transistor is an N-type metal oxide semiconductor (NMOS) transistor. 
     
     
         11 . The comparator of  claim 7 , wherein the clamp circuit further comprises a second enable switch, coupled between the second clamp transistor and a power supply terminal of the comparator. 
     
     
         12 . The comparator of  claim 7 , wherein the second clamp transistor clamps the second output signal to have a lower limit higher than a ground voltage. 
     
     
         13 . The comparator of  claim 1 , wherein the gain stage comprises a high-side transistor and a low-side transistor, and the low-side transistor keeps on when the second output signal is at a high level and when the second output signal is at a low level. 
     
     
         14 . An image sensing circuit, having a plurality of input channels, the image sensing circuit comprising:
 a ramp generator to generate a ramp signal; and   a plurality of comparators, each comprising:
 an input stage, coupled to the ramp generator and one of the plurality of input channels, to receive an input signal from the coupled input channel and receive the ramp signal from the ramp generator, and generate a first output signal; 
 a gain stage, coupled to the input stage, to receive the first output signal and generate a second output signal; 
 an output stage, coupled to the gain stage, to receive the second output signal and generate a third output signal; and 
 a clamp circuit, coupled to the gain stage and the output stage. 
   
     
     
         15 . The image sensing circuit of  claim 14 , wherein the gain stage comprises a high-side transistor and a low-side transistor, and the clamp circuit comprises:
 a first clamp transistor, coupled between the high-side transistor and a power supply terminal of the comparator.   
     
     
         16 . The image sensing circuit of  claim 15 , wherein a drain terminal of the first clamp transistor is coupled to the high-side transistor, a source terminal of the first clamp transistor is coupled to the power supply terminal, and a gate terminal of the first clamp transistor is coupled to an output terminal of the gain stage. 
     
     
         17 . The image sensing circuit of  claim 15 , wherein the first clamp transistor is a P-type metal oxide semiconductor (PMOS) transistor. 
     
     
         18 . The image sensing circuit of  claim 15 , wherein the clamp circuit further comprises a first enable switch, coupled between the first clamp transistor and the power supply terminal. 
     
     
         19 . The image sensing circuit of  claim 15 , wherein the first clamp transistor clamps the second output signal to have an upper limit lower than a power supply voltage of the comparator. 
     
     
         20 . The image sensing circuit of  claim 14 , wherein the clamp circuit comprises:
 a second clamp transistor, coupled between the gain stage and the output stage.   
     
     
         21 . The image sensing circuit of  claim 20 , wherein a first terminal of the second clamp transistor is coupled to an output terminal of the gain stage, a second terminal of the second clamp transistor is coupled to a power supply terminal of the comparator, and a gate terminal of the second clamp transistor is coupled to the output stage. 
     
     
         22 . The image sensing circuit of  claim 20 , wherein the second clamp transistor is a PMOS transistor. 
     
     
         23 . The image sensing circuit of  claim 20 , wherein the second clamp transistor is an N-type metal oxide semiconductor (NMOS) transistor. 
     
     
         24 . The image sensing circuit of  claim 20 , wherein the clamp circuit further comprises a second enable switch, coupled between the second clamp transistor and a power supply terminal of the comparator. 
     
     
         25 . The image sensing circuit of  claim 20 , wherein the second clamp transistor clamps the second output signal to have a lower limit higher than a ground voltage. 
     
     
         26 . The image sensing circuit of  claim 14 , wherein the gain stage comprises a high-side transistor and a low-side transistor, and the low-side transistor keeps on when the second output signal is at a high level and when the second output signal is at a low level. 
     
     
         27 . The image sensing circuit of  claim 14 , further comprising:
 a plurality of counters, each coupled to an output terminal of one of the plurality of comparators.