Radio frequency (rf) variable gain amplifier (vga) with varying gain elements

Abstract

Aspects include amplifiers with different units for improved performance. One amplifier has a first transistor with first gate is coupled to a control input, and a first drain is coupled to a first terminal of an output, a second transistor with a second gate is coupled to the control input, and a second drain is coupled to a second terminal of the output. The amplifier has a third transistor with a third drain coupled to the first transistor source, and a third gate is coupled to a first terminal of an input, and a fourth transistor with a fourth drain is coupled to the second transistor source, and a fourth source gate is coupled to a second terminal of the input, where the first transistor source is not connected to the second transistor drain via one or more transistors.

1 . A radio frequency (RF) variable gain amplifier (VGA) comprising:
 a first transistor comprising a first gate, a first source, and a first drain, wherein the first gate is coupled to a control input, and wherein the first drain is coupled to a first terminal of an output;   a second transistor comprising a second gate, a second source, and a second drain, wherein the second gate is coupled to the control input, and wherein the second drain is coupled to a second terminal of the output;   a third transistor comprising a third gate, a third source, and a third drain, wherein the third drain is coupled to the first source, and wherein the third gate is coupled to a first terminal of an input; and   a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled to the second source, and wherein the fourth gate is coupled to a second terminal of the input;   wherein the first source is not connected to the second drain via one or more transistors, and wherein the second source is not connected to the second drain via one or more transistors.   
     
     
         2 . The RFVGA of  claim 1 , comprising a plurality of VGA units, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor comprise a first VGA unit, wherein the first source is not connected to the second drain via one or more transistors, and wherein the second source is not connected to the second drain via one or more transistors to limit parasitics for signal path splitting, wherein half the plurality of VGA units include most significant bit (MSB) switches, and wherein each VGA unit of the plurality of VGA units includes cascode control switching. 
     
     
         3 . The RFVGA of  claim 1 , further comprising a transformer comprising a first input, a second input, a first output, and a second output, wherein the first input is coupled to the first terminal of the output, wherein the second input is coupled to the second terminal of the output. 
     
     
         4 . The RFVGA of  claim 1 , wherein the third source and the fourth source are coupled to a reference voltage node. 
     
     
         5 . The RFVGA of  claim 1 , further comprising:
 a fifth transistor comprising a fifth source, a fifth drain, and a fifth gate, wherein the fifth source is coupled to the first source, wherein the fifth gate is coupled to a second control input, and wherein the fifth drain is coupled to a voltage power node; and   a sixth transistor comprising a sixth source, a sixth drain, and a sixth gate, wherein the sixth source is coupled to the second source, wherein the sixth gate is coupled to the second control input, and wherein the sixth drain is coupled to the voltage power node.   
     
     
         6 . The RFVGA of  claim 1 , further comprising a plurality of parallel VGA amplifier units, wherein a first unit of the plurality of parallel VGA amplifier units comprises the first transistor, the second transistor, the third transistor, and the fourth transistor. 
     
     
         7 . The RFVGA of  claim 6 , wherein a second unit of the plurality of parallel VGA amplifier units comprises:
 a first transistor comprising a first gate, a first source, and a first drain, wherein the first gate is coupled to a third control input, and wherein the first drain is coupled to a first terminal of an output;   a second transistor comprising a second gate, a second source, and a second drain, wherein the second gate is coupled to the third control input, and wherein the second drain is coupled to a second terminal of the output;   a third transistor comprising a third gate, a third source, and a third drain, wherein the third drain is coupled to the first source, and wherein the third gate is coupled to a first terminal of an input;   a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled to the second source, and wherein the fourth gate is coupled to a second terminal of the input;   a fifth transistor comprising a gate, a source, and a drain, wherein the gate is coupled to a fourth control input, wherein the source is coupled to the first source, and wherein the drain is coupled to the second drain; and   a sixth transistor comprising a gate, a source, and a drain, wherein the gate is coupled to the fourth control input, wherein the source is coupled to the second source, and wherein the drain is coupled to the first drain.   
     
     
         8 . The RFVGA of  claim 7  wherein the plurality of parallel VGA amplifier units includes a first plurality of units of a first type comprising the first unit, and a second plurality of units of a second type comprising the second unit. 
     
     
         9 . The RFVGA of  claim 1 , wherein the first terminal of the input is coupled to a first bias node via a first resistive element, and wherein the second terminal of the input is coupled to a second bias node via a second resistive element. 
     
     
         10 . The RFVGA of  claim 1 , wherein the RFVGA is configured in a first path of a split transmission path of a phased array transmission system. 
     
     
         11 . The RFVGA of  claim 1 , wherein the first transistor and the second transistor are not connected via cross coupled most significant bit (MSB) switches. 
     
     
         12 . A wireless communication apparatus comprising:
 a phased array transmission circuit comprising a plurality of split signal paths, wherein a first path of the plurality of split signal paths comprises a first radio frequency (RF) variable gain amplifier (VGA), the first RFVGA comprising:   a first transistor comprising a first gate, a first source, and a first drain, wherein the first gate is coupled to a control input, and wherein the first drain is coupled to a first terminal of an output;   a second transistor comprising a second gate, a second source, and a second drain, wherein the second gate is coupled to the control input, and wherein the second drain is coupled to a second terminal of the output;   a third transistor comprising a third gate, a third source, and a third drain, wherein the third drain is coupled to the first source, and wherein the third gate is coupled to a first terminal of an input; and   a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled to the second source, and wherein the fourth gate is coupled to a second terminal of the input;   wherein the first source is not connected to the second drain via one or more transistors, and wherein the second source is not connected to the second drain via one or more transistors.   
     
     
         13 . The wireless communication apparatus of  claim 12 , further comprising:
 transceiver circuitry coupled to the first terminal of the input and the second terminal of the input; and   an antenna element coupled to the first terminal of the output and the second terminal of the output.   
     
     
         14 . The wireless communication apparatus of  claim 12 , further comprising a plurality of VGA units, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor comprise a first VGA unit, wherein the first source is not connected to the second drain via one or more transistors, and wherein the second source is not connected to the second drain via one or more transistors to limit parasitics for signal path splitting, wherein half the plurality of VGA units include MSB switches, and wherein each VGA unit of the plurality of VGA units includes cascode control switching. 
     
     
         15 . The wireless communication apparatus of  claim 12 , wherein the third source and the fourth source are coupled to a reference voltage node. 
     
     
         16 . The wireless communication apparatus of  claim 12 , further comprising:
 a fifth transistor comprising a fifth source, a fifth drain, and a fifth gate, wherein the fifth source is coupled to the first source, wherein the fifth gate is coupled to a second control input, and wherein the fifth drain is coupled to a voltage power node; and   a sixth transistor comprising a sixth source, a sixth drain, and a sixth gate, wherein the sixth source is coupled to the second source, wherein the sixth gate is coupled to the second control input, and wherein the sixth drain is coupled to the voltage power node.   
     
     
         17 . The wireless communication apparatus of  claim 14 , wherein a second VGA unit of the plurality of VGA units comprises:
 a first transistor comprising a first gate, a first source, and a first drain, wherein the first gate is coupled to a third control input, and wherein the first drain is coupled to a first terminal of an output;   a second transistor comprising a second gate, a second source, and a second drain, wherein the second gate is coupled to the third control input, and wherein the second drain is coupled to a second terminal of the output;   a third transistor comprising a third gate, a third source, and a third drain, wherein the third drain is coupled to the first source, and wherein the third gate is coupled to a first terminal of an input;   a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled to the second source, and wherein the fourth gate is coupled to a second terminal of the input;   a fifth transistor comprising a gate, a source, and a drain, wherein the gate is coupled to a fourth control input, wherein the source is coupled to the first source, and wherein the drain is coupled to the second drain; and   a sixth transistor comprising a gate, a source, and a drain, wherein the gate is coupled to the fourth control input, wherein the source is coupled to the second source, and wherein the drain is coupled to the first drain.   
     
     
         18 . A radio frequency (RF) variable gain amplifier (VGA) comprising an RFVGA unit in a folded configuration, the RFVGA unit comprising:
 a first transistor comprising a first gate, a first source, and a first drain, wherein the first gate is coupled to a control input, wherein the first source is coupled to a first terminal of an output, and wherein the first drain is coupled to a voltage source via a first resistive element;   a second transistor comprising a second gate, a second source, and a second drain, wherein the second gate is coupled to the control input, wherein the second source is coupled to a second terminal of the output and wherein the first second drain is coupled to the voltage source via a second resistive element;   a third transistor comprising a third gate, a third source, and a third drain, wherein the third drain is coupled to the first drain, and wherein the third gate is coupled to a first terminal of an input; and   a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain, wherein the fourth drain is coupled to the second drain, and wherein the fourth gate is coupled to a second terminal of the input.   
     
     
         19 . The RFVGA of  claim 18 , wherein the third source is coupled to a reference voltage, and wherein the fourth source is coupled to the reference voltage. 
     
     
         20 . The RFVGA of  claim 19 , wherein the RFVGA unit further comprises:
 a fifth transistor comprising a fifth gate, a fifth source, and a fifth drain, wherein the fifth drain is coupled to the voltage source, the fifth gate is coupled to a second control input, and wherein the fifth source is coupled to the first source of the first transistor and to the first terminal of the output; and   a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain, wherein the sixth drain is coupled to the voltage source, the sixth gate is coupled to the second control input, and wherein the sixth source is coupled to the second source of the second transistor and to the second terminal of the output.